High Throughput and Low Complexity Implementation For Uplink Scheme of 5G Technology

High Throughput and Low Complexity
Implementation for Uplink Scheme of

5G Technology
University of Information Technology, VNU-HCM
9/24/2019 Copyrights 2019 UIT-CE Wireless Communication R&D Group . All Rights Reserved. 1
CONTENT
 Introduction
 Proposed SCMA encoder/decoder
 Simulated and Hardware Implementation Results
 Conclusion
Introduction
 Today, 5G technology is being urgently completed and

implemented, to bring users improvements over current
4G technology:
Higher speed (20Gb/s).
Smaller delay (<1ms).
Great number of connection (100k connection/km2).
 To handle this issue, non-orthogonal multiple access
(NOMA) has been considered as a ideal candidate to
address the challenges for 5G.
Introduction
Multiple Access
Techniques
OMA NOMA(5G)
Power-Domain
TDMA(2G) CDMA(3G) SIC SCMA
FDMA(2G) OFDMA(4G) LDS-CDMA PDMA
LDS-OFDM BOMA
Multiple access techniques TCMA IDMA
Introduction
 Conventional SCMA [3]

Based on the message passing algorithm (MPA)
Very high complexity implementation
Cost a lot of hardware resources
 Proposed SCMA
Based on the euclidean distance and the binding relationship
between users
Reduce the complexity implementation
Reduce the cost of hardware resources
Increase transmission bandwidth
Keep BER performance compared to the conventional SCMA
Introduction
 Overview architecture of the Design:

y = x1h1+ x2h2 + x3h3 + x4h4 + x5h5 + x6h6 + n
LDPC
SCMA
Data bits
encoded
bits codeword
Channel
x1 h1
USER 1
LDPC s1 SCMA s1 LDPC USER 1
ENCODER ENCODER DECODER Data bits
h2
LDPC s2 SCMA x2 s2 LDPC USER 2
USER 2
h3
s3
LDPC SCMA x3 s3 LDPC USER 3
USER 3
ENCODER ENCODER h4 DECODER Data bits
y SCMA
LDPC
s4 SCMA
x4 h5
DECODER
s4 LDPC USER 4
USER 4
ENCODER ENCODER Data bits
n DECODER
h6
LDPC
s5 SCMA x5 s5 LDPC USER 5
USER 5
LDPC
s6 SCMA
x6 s6 LDPC USER 6
USER 6
Proposed SCMA Encoder
 SCMA:
Input bits are directly mapped and spread into resources.
Over resources (channel) loading increases transmission speed
Sparsity: low complexity on decoding.
 Spared_QPSK: UE1 UE2 UE3
01 11 00 01 10 11 00 01 10 11 00 01 10 11
RE1
RE2 0 0 0 0 0 0 0 0
RE3 0 0 0 0 0 0 0 0
RE4 0 0 0 0 0 0 0 0
00 10
UE1 UE2 UE3 UE4 UE5 UE6

2
0
-3 -2 -1 0 1 2 3
-1 RE1 RE2 RE3 RE4
-2
-3
 SCMA Coding flow:
Proposed SCMA Encoder 01 11
 Detail of coding flow:

00 10
Super-position matrix
(performed on channel)
Hardware Implementation
ROM_b00 CB_b00
/CB_01
ROM_b01 /CB_10
/CB_11
Resource1_CodedBit
ROM_b10
ROM_b11
Modulated_Symbol_Selection
Resource1_Selection
Resource2_CodedBit
Resource2_Selection
Binary Input Data Controller Resource3_Selection Resource3_CodedBit
User Infor
Resource4_Selection
Resource4_CodedBit
Proposed SCMA Decoder
Hardware Implementation
Stage 1 Stage 2 Stage 3
Iteration (N)
yResource_1 Calculation of Expected Decoding Expected

Euclidean _ x{u1,u2,u3} Resource_1 _s{u1,u2,u3}
Distance
yResource_2 Expected
_s{u1,u4,u5}
Resource Expected
…
…
compare _s{u1,u2,u3,u4,u5,u6}
yResource_3 Expected module
_s{u2,u4,u6}
Calculation of Decoding Expected

Expected
yResource_4 Euclidean _ x{u3,u5,u6} Resource_4 _s{u3,u5,u6}
Distance
Proposed Pipeline Processing
 We pipelined 2-level for the design to increase the

speed.
Simulation Result
 BER 0
10
-1
10
-2
10
BER
-3
10
-4
10
10
-5 Conventional Hardware Implementation [3]
Proposed Hardware Implementation
Proposed Matlab Implementation
-6
10
2 4 6 8 10 12 14 16
Eb/No(dB)
Hardware Implementation Result
 Throughput of the design with F = 47.78 MHz:

100
Conventional Implementation [3]
Our Proposed Implementation
80
Throughput (Mbps)
60
40
23.89
20.2
20
0
Hardware Implementation Result
 Hardware resource:
Conventional Design Proposed Design
LUTs 15,195 9,204
Registers 4,936 3,472
Conclusions
 Improve bandwidth efficiency by using spared

modulation
 Cost less hardware resources, but the BER accuracy of
decoding is a bit lower.
 Improve processing time nearly 2 times by the 2-level
pipeline implementation
References
 [1] K. Pandya, Comparative Study on Wireless Mobile Technology: 1G, 2G, 3G, 4G and 5G, Gujarat
Technological University, Gujarat, India.
 [2] M. Agiwal, A. Roy and N. Saxena, "Next Generation 5G Wireless Networks: A Comprehensive Survey," in
IEEE Communications Surveys & Tutorials, vol. 18, no. 3, pp. 1617-1655, thirdquarter 2016.
 [3] Yunfei Wu, Jincheng Dai, Kai Niu, Chao Dong and Xin Bian, Hardware Design and Implementation of
Sparse Code Multiple Access, Key Laboratory of Universal Wireless Communications, Ministry of Education,
Beijing University of Posts and Telecommunications, Beijing, China 100876.
 [4] H. Nikopour and H. Baligh, “Sparse code multiple access,” in Proc.IEEE PIMRC 2013, pp. 332-336, Sep.
2013.
 [5] U. Koc, A. Leven, Y. Chen and N. Kaneda, "Digital coherent quadrature phase-shift-keying (QPSK)," 2006
Optical Fiber Communication Conference and the National Fiber Optic Engineers Conference, Anaheim, CA,
2006, pp. 3 pp.-.
 [6] Z. Wei, J. Guo, D. W. K. Ng and J. Yuan, "Fairness Comparison of Uplink NOMA and OMA," 2017 IEEE
85th Vehicular Technology Conference (VTC Spring), Sydney, NSW, 2017, pp. 1-6.
 [7] Y. Saito, Y. Kishiyama, A. Benjebbour, T. Nakamura, A. Li, and K. Higuchi, “Non-orthogonal multiple
access (NOMA) for cellular future radio access” in Proc. IEEE Veh. Tech. Conf., Dresden, Germany, Jun. 2013.
 [8] Lizhong Zheng, D. Tse and M. Medard, "On the costs of channel state information," Information Theory
Workshop, San Antonio, TX, USA, 2004, pp. 423-427.
 [9] Z. Tu and S. Zhang, "Overview of LDPC Codes," 7th IEEE International Conference on Computer and
Information Technology (CIT 2007), Aizu-Wakamatsu, Fukushima, 2007, pp. 469-474.

High Throughput and Low Complexity Implementation For Uplink Scheme of 5G Technology

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High Throughput and Low Complexity Implementation For Uplink Scheme of 5G Technology

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High Throughput and Low Complexity

Implementation for Uplink Scheme of

 Today, 5G technology is being urgently completed and

FDMA(2G) OFDMA(4G) LDS-CDMA PDMA

Multiple access techniques TCMA IDMA

 Conventional SCMA [3]

 Overview architecture of the Design:

UE1 UE2 UE3 UE4 UE5 UE6

-1 RE1 RE2 RE3 RE4

 SCMA Coding flow:

 Detail of coding flow:

yResource_1 Calculation of Expected Decoding Expected

Calculation of Decoding Expected

 We pipelined 2-level for the design to increase the

 Throughput of the design with F = 47.78 MHz:

Conventional Design Proposed Design

LUTs 15,195 9,204

Registers 4,936 3,472

 Improve bandwidth efficiency by using spared

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