UNIT-VIII

CMOS TESTING
INTRODUCTION:
•After the chip fabricated it is tested for manufacturing
defects.
•Verification is related to formal proof of correctness.
•Validation is technique that increase confidence in
correctness.
“If you don’t test it, it won’t work!”
NEED FOR TESTING
 During fabrication process several types of defects may
exists such as
Catastropic
Crystalline
Catastropic defect is due to contamination,resulting in
destruction of all the transistors on the chip.
Crystalline defect is because of destruction of a single
transistor on the chip.
Functionality Tests:
 First tests performed during design process.
It ensure that all the gates in the chip, acting in concert and
achieve a desired function to verify the functionality of the
circuit.
Manufacturing Tests:
It verify that every gate operates as expected.
It occurs during chip fabrication or during accelerated life
testing.
It verify each gate and register is operational. These tests
are carried out at wafer level, to reject bad die.
TEST PRINCIPLES:
N inputs N outputs
Combinational logic

2n inputs required to test the circuit

N inputs N outputs

Combinational logic

M inputs clk M outputs

Register

2n +m inputs required to test the circuit

FAULT MODELS
• A model for how faults occur and their impact on
circuits is called a fault model.
Two popular fault models are:
1.Struck-at-Faults
» Struck-at-One
» Struck-at-Zero
2.Struck-at-Open or stuck-short faults
• Faults most frequently occur due to thin-oxide shorts or
metal-to-metal shorts.
Struck-at-0 fault:
OBSERVABILITY:
• The observability of a particular internal circuit node is the degree to
which one can observe that node at the outputs of an integrated
circuits.
• Poor observability includes sequential circuits with long feedback
100ps.
CONTROLLABILITY:
• The controllability of an internal circuit node within a chip is a measure
of the ease of setting the node to a 1 or 0 state.
• Controllability is important while accessing the degree of difficulty of
testing a particular signal in a circuit.
• A node with little controllability may take hundreds of cycles to get it
to the right state.
FAULTY COVERAGE:
• The percentage of fault that can be detected by the applied test vector.
• Fault coverage gives a measure of goodness of test program
• Design for Testability (DFT) is used to improve the fault coverage..
FAULT SIMULATION:
 The process of measuring the quality of test. Fault simulation is
performed using gate level model and functional level model.
Fault simulation serves following functions:
1. Confirms detection of fault.
2. Computes fault coverage.
3. Diagnostic of circuit.
4. Identifies areas of circuit where fault coverage is inadequate.
DESIGN STRATEGIES FOR TEST
DESIGN FOR TESTABILITY:
 Design for testability shows the fault model to test the chip in
manufacturing process.
 Design for testability covers three important approaches
1. Ad-hoc testing
2. Scan based approaches
3. Self-test and built in testing
Scan Path:
• A scan path is a DFT which involves specialized flip-flop or
latch allowing data to be scanned in for control and then out
for observation and then activated in scan mode for test
purposes.
• A scan path is tested by shifting pattern through the scan path
before stuck at faults begins.
• A scan path consists of placing a multiplexer just ahead of
each flip-flop
Fig. Scan path
Fig. Scan shift operation
Advantages:
 Test vector can be generated by automatic test pattern generator.
 During design phase problems like observability and controllability
need not to be consider.
 No need of complex test vector generator for all inputs except scan in
and scan out.
Disadvantages:
 Scan path results in hardware overhead as additional multiplexers are
required.
 Speed degradation may be observed due to additional multiplexers in
signal path.
Full Scan and partial Scan
Full Scan:
 Sequential ATPG is used for partial scan and combinational
ATPG is used for full scan.
 Full scan provides total controllability and observability.
 Full scan provides high fault coverage for structural defects.
Full scan testing is carried out in two phases:
Phase-1: It tests the scan register by a shift test.
Phase-2: Single stuck-at faults in combinational logic.
 The test generation time is very small for full scan.
Partial Scan:
 In partial scan mode all the FFs are not into a scan path.

Fig. Partial scan

 It improves the fault coverage and fault efficiency to

adequately high level.
CHIP LEVEL AND SYSTEM LEVEL TEST TECHNIQUES
Boundary Scan Check:
• It is a test technique which uses scan methodology involving shift
registers. The shift register control monitors signal at each input ad
output pins that are connected in serial fashion to form a chain of data
register called Boundary Scan Registers.
• PCBs are more dense and complex.
Merits:
1. Increased fault coverage in system.
2. More time efficient.
3. The process is very simple.
Boundary scan standards:
1.JTAG
2. Element Test and Maintenance
3. VHSIC Test and Maintenance
4. Testability Bus Standard PackageInterconnect

CHIP B CHIP C

Serial Data Out

CHIP A CHIP D

IO pad and Boundary Scan

Cell

Serial Data In
• The boundary scan path is having serial input output cells/pads and
has appropriate clock pads. The cells or pads are provided for
a) Interconnections between chips.
b) Internal self test.
Various tests that carried out by the architecture IEEE 1149 are
a) Sampling and setting chip input/outputs.
b) Connectivity test between components.
Distribution and collection of self test and built in test.
JTAG:
• It verify whether the circuit has been mounted on circuit board
correctly. JTAG specifies method to test device functionality and
interconnections through TAP and boundary scan.
• BIST mode is used to limit the number of vectors that need to be
clocked through the scan path. BIST mode generates PRTV as stimuli
compares internal outputs against expected results and indicates
success or failures.
JTAG internal circuit:

• JTAG to test internal output failures.

• Use of JTAG to test internal circuitry.

Fig. JTAG for testing internal testing

JTAG for External Testing:
• JTAG used for external testing of connections to other JTAG devices.

Fig. JTAG for external testing

• JTAG Architecture: