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Houston Impact of J-STD-001F and IPC-A-610F Changes
Houston Impact of J-STD-001F and IPC-A-610F Changes
Houston Impact of J-STD-001F and IPC-A-610F Changes
AAI Corporation
Agenda
• J-STD-001F
– What’s New
– Additions
• IPC-A-610F
– What’s New
– Additions
• Training
A New Revision of J-STD-001
• What’s New?
– Format
• Removed Space Shuttle symbol
– Layout
• Some requirements relocated for readability
– Revised Requirements
• Where data supported a change
– New Requirements
• To support industry advance
J-STD-001 Terms & Definitions
FOD
Un-supported holes with spacer not in full contact. Defect Defect Defect
No
Spacer is inverted. Defect Defect
Requirement
Hold Down of Surface Mount
Leads/Components
Table 7-4 Plated-Through Holes with Component Leads , Minimum Acceptable Solder Conditions1
Criteria Class 1 Class 2 Class 3
Vertical fill of solder for component with less than 14
75%
leads, Notes 2 and 3 (see 7.3.5.1).
75%
A Not specified 50% or 1.2 mm
Vertical fill of solder for component with 14 leads or [0.05 in],
more. Notes 2 and 3 and Figure 6-4 whichever is
less
Note 1: Wetted solder refers to solder applied by any solder process including intrusive soldering. For intrusive
soldering there may not be an external fillet between the lead and the land
Note 2: The 25% unfilled height includes the sum of both source and destination side depressions
Note 3: Less than 100% solder fill may not be acceptable in some applications, e.g., thermal shock, electrical
performance
Chip Components – Billboarding
• Same as J-STD-001F
P-Style Connections
(NEW)
• Same as J-STD-001F
9.2 Chip Resistor Element
• Acceptable – Class 1, 2, 3
– No damage to the resistive element or glass coating.
– No exposure of the resistive element.
• Reference to 1206 size component removed.
9.13 Threaded Items and
Hardware (NEW)
• Removed the laser and wand type scanner and replaced with
code can be read with 3 or fewer attempts.
10.8.4 Electrical Insulation
Coating (NEW)