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Universal Asynchronous Receiver and Transmitter
Universal Asynchronous Receiver and Transmitter
Universal Asynchronous Receiver and Transmitter
NAME-
SUBHANGI MODGIL(102)
SONY KUMARI(109)
SHAILJA PANDEY(95)
SIMRAN KUMARI(105)
SHIVANI SUMAN(97) 1
CONTENTS
INTRODUCTION TO UART
BASICS OPF SERIAL
COMMUNICATION-RS-232
BASIC BLOCK DIAGRAM
OF UART
TRANSMITTER CONTD.
RECEIVER CONTD.
UART REGISTERS
UART CHARACTER
TRANSMISSION
WHERE DO WE CODE?
APPLICATIONS CONTD.
WHY WE USE UART ?
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ACKNOWLEDGEMENT
We would like to thank the HOD of E.C.E
department “DR.VED PRAKASH ROY” who
provided us an opportunity to explore and prepare
a presentation on the topic “UNIVERSAL
ASYNCHRONOUS RECEIVER
TRANSMITTER”.
We would also like to thank all faculty members
for their support and help in preparing this
presentation.
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INTRODUCTION OF UART
UART-STANS FOR UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
USART –STANDS FOR UNIVERSAL ASYNCHORONOUS
RECEIVER TRANSMITTER
IN RS-232 WE IMPLEMENT SERIAL ;PORT
WITH UART
ACTUALLY UART RECEIVES/SENDS DATA TO
MICROPROCESSOR /MICROCONTROLLER THROUGH DATA
BUS.THE REMAINING PART OF SIGNAL HANDLING OF RS-
232IS DONE BY UARTI.E.START BIT,STOP BIT,PARITY ETC.
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BASIC OF SERIAL COMMUNICATION
BIT RATE :
-NUMBER OF BITS SENT EVERY SECOND(BPS)
BAUD RATE:
-NUMBER OF SYMBOLS SENT EVERY SECOND,WHERE
EVERY SYMBOL CAN REPRESENT MORE THAN ONE BIT.
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SERIAL COMMUNICATION
BLOCK DIAGRAM
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SERIAL/RS-232 PORT ON PC &ITS
PIN OUT
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EIA RS232C SERIAL INTERFACE
STANDARD
A “SPACE “(LOGIC 0) WILL BE BETWEEN 3 AND 25 VOLTS .
A “MARK”(LOGIC 1) WILL BE BETWEEN -3 AND -25 VOLTS.
THE REGION BETWEEN 3 AND -3 VOLTS IS UNDEFINED.
MAXIMUN DATA RATES MAY BE UPTO 20kbps.
MAXIMUM SERIAL CABLE LENGTH MAY BE 15 METERS.
REASON TO STUDY RS-232C IS THAT THE SRTIAL PART
FOUND IN PC’S USES THIS STANDARDS.
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RS-232 PIN ASSIGNMENT
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BASIC BLOCK DIAGRAM
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TRANSMITTER CONTD.
TXIF BIT : IN THE PIR1 REGISTERS
TRMT BIT:
1. ONCE THE DATA IN THE TSR REGISTER HAS BEEN CLOCKED OUT
ON THE TX PIN (AT THE BEGINNING OF THE STOP BIT ),THE TRMT
BIT IN THE TXSTA REGISTER WILL BE SET ,
2. INDICATING THAT THE TRANSMISSION HAS BEEN COMPLETED.
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TRANSMITTER BLOCK DIAGRAM
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RECEIVER CONTD.
1. EVERY RECEIVED BIT IS SAMPLED AT THE MIDDLE OF THE BIT’S
TIME PERIOD.
2. UART CAN BE CONFIGURED TO RECEIVE EIGHT OR NINE BITS BY
THE RX9 BIT IN THE RCSTA REGISTER.
3. AFTER THE DETECTION OF A START BIT,EIGHT OR NINE BITS OF
SERIAL DATA ARE SHIFTED FROM THE RX PIN INTO THE RECEIVE
SHIFT REGISTER, ONE BIT AT A TIME.
4. AFTER THE LAST BIT HAS BEEN SHIFTED IN,THE STOP BIT IS
CHECKED AND THE DATA IS MOVED INTO THE FIFO BUFFER.
5. RCREG IS THE OUTPUT OF THE TWO ELEMENT FIFO BUFFER. A
NEXT START BIT CAN BE SENT IMMEDIATELY AFTER THE STOP BIT.
6. RCIF:INDICATES WHEN DATA IS AVAILABLE IN THE RCREG.
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RECEIVER BLOCK DIAGRAM
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UART REGISTERS
TO USE AND CONTROL THE UART ,SPECIAL INTERNAL REGISTERS
ARE ASSIGNED TO THEM.USUALLY THERE WILL BE ATLEAST FOUR
REGISTERS,THEY ARE:-
1. CONTROL REGISTER :-CONTAINS SETTINGS FOR THE UART.
SOME COMMON SETTINGS INCLUDE :
-NUMBER OF DATA BITS
-NUMBER OF STOP BITS
-PARITY CONTROL
2. STATUS REGISTER :-THIS CONTAINS INFORMATION ABOUT THE
UARTS CONDITION OR STATE
3. RECEIVE REGISTER:- THIS IS THE WHERE RECEIVED DATA IUS
TEMPORARILY STORED.
4. TRANSMIT REGISTER :-A BUFFER REGISTER FOR TEMPORARILY
STORING DATA TO BE SENT.
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UART CHARACTER TRANSMISSION
BELOW IS A TIMING DIAGRAM FOR THE TRANSMISSION OF
A SINGLE BYTE
USES A SINGLE WIRE FOR TRANSMISSION
EACH BLOCK REPRESENTS A BIT THAT CAN BE A MARK
(LOGIC ‘1) OR SPACE (LOGIC’0’)
1 Bit
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WHERE DO WE CODE ??
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APPLICATIONS CONTD.
PC SERIAL PORT IS A UART !
-SERIALIZES DATA TO BE SENT OVER SRIAL CABLE
-DE-SERIALIZES RECEIVED DATA
THE UART IS ALSO RESPONSIBLE FOR BAUD RATE GENERATION.
THIS DETERMINES THE SPEED AT WHICH DATA IS TRANSMITTED AND
RECEIVED.
1 BAUD RATE =1BIT/SEC(BPS)
WITH MODEM UARTS ,230,400 BAUD CAN BE ACHIEVED WITH A SHORT
CABLE LENGTH OF A FEW FEET.
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APPLICATIONS OF UART
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WHY WE USE UART??
A UART MAY BE USED WHEN:
-HIGH SPEED IS NOT REQUIRED
-AN INEXPENSIVE COMMUNICATION LINK BETWEEN TWO
DEVICES IS REQUIRED.
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ADVANTAGES & DISADVANTAGES
OF UART
ADVANTAGES: DISADVANTAGES:
-USES TWO WIRES -THE SIZE OF THE DATA
-NO CLOCK SIGNAL IS FRAME IS LIMITED(MAX 9
NECESSARY BITS).
-HAS A PARITY BIT -DOESN’T SUPPORT
MULTIPLE MASTER SYSTEM
-WELL DOCUMENTED
.
AND WIDELY USED
METHOD. -BAUD RATE OF EACH
UART MUST BE WITHIN 10%
OF EACH OTHER.
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CONCLUSION
THIS ARTICLE HAS COVERED SOME DETAILS ABOUT A
COMMUNICATION PROTOCOL, THAT WE SUCCESSFULLY
USED MANY TIMES.IT IS POSSIBLE TO IMPLEMENT A UART
INTERFACE WHILE KNOWING VERY LITTLE ABOUT THE
ACTUAL BEHAVIOUR OF THE SIGNALS AND HARDWARE-
ASIDE FROM THE GENERAL EDIFICATION THAT SUCH
KNOWLEDGE PROVIDES –CAN BE HELPFUL .
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BIBLIOGRAPHY
“UNIVERSAL ASYNCHRONOUS RECEIVER
TRANSMITTER”(2018,NOVEMBER) references
taken from
BOOK-ESSENTIAL GUIDE TO
TELECOMMUNICATION
AUTHOR-ANNABEL DODD
http://google.com/universalasynchronousreceivertr
ansmittertheory
http://knowledgeworld.com/
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