Static Sequential Circuits

Sequential Logic

Inputs Outputs
Combinational
Logic

Current Next
State State

clock
Timing Metrics

clock
clock

tsu thold time

In data
stable
tc-q time

Out output output

stable stable
time
System Timing Constraints

Inputs Outputs
Combinational
Logic

Current Next
State State

T (clock period)
clock

tcdreg + tcdlogic  thold T  tc-q + tplogic + tsu

Static vs Dynamic Storage

 Static storage
 preserve state as long as the power is on
 have positive feedback (regeneration) with an internal
connection between the output and the input

 Dynamic storage
 store state on parasitic capacitors
 only hold state for short periods of time (milliseconds)
 require periodic refresh
 usually simpler, cheaper with higher density
Latches vs Flipflops

 Latches
 level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode
 input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode

 Flipflops (edge-triggered)
 edge sensitive circuits that sample the inputs on a clock
transition
- positive edge-triggered: 0  1
- negative edge-triggered: 1  0
 built using latches (e.g., master-slave flipflops)
Positive and Negative Latches

clock clock

clk clk

In In

Out Out
Review: The Regenerative Property
Vi1 Vo1 Vi2 Vo2

cascaded inverters

A If the gain in the transient

region is larger than 1,
C
only A and B are stable
operation points. C is a
metastable operation
B point.
Vi1 = Vo2
Bistable Circuits
 The cross-coupling of two Vi1
inverters results in a bistable
circuit (a circuit with two Vi2
stable states)

 Have to be able to change the stored value by making A

(or B) temporarily unstable by increasing the loop gain to
a value larger than 1
 done by applying a trigger pulse at Vi1 or Vi2
 the width of the trigger pulse need be only a little larger than the
total propagation delay around the loop circuit (twice the delay of
an inverter)

 Two approaches used

 cutting the feedback loop (mux based latch)
 overpowering the feedback loop (as used in SRAMs)
Review: SR Latch

S R Q !Q
S 0 0 Q !Q memory
!Q
1 0 1 0 set

0 1 0 1 reset
Q
R 1 1 0 0 disallowed
Review : Clocked D Latch

D
!Q

Q
D Q

clock

transparent mode clock

clock

hold mode
MUX Based Latches
 Change the stored value by cutting the feedback loop

feedback feedback

1 0
Q Q
D 0 D 1

clk clk

Negative Latch Positive Latch

Q = clk & Q | !clk & D Q = !clk & Q | clk & D

transparent when the transparent when the
clock is low clock is high
TG MUX Based Latch Implementation

clk

!clk

input sampled
D (transparent mode)

clk
clk
D Q
!clk

clk feedback
(hold mode)
PT MUX Based Latch Implementation

clk !Q

D Q

input sampled
(transparent mode)
!clk

 Reduced area and clock clk

load, but a threshold drop
!clk
at output of pass transistors
so reduced noise margins
and performance feedback
(hold mode)
Latch Race Problem

B
B B’

clk

Which value of B is stored?

clk

Two-sided clock constraint

T  tc-q + tplogic + tsu
Thigh  tc-q + tcdlogic
 Master Slave Based Flipflop

D Q

0
1 Q clock
1
QM
D 0
clk clk
clk
Slave D
Master

clk = 0 transparent hold QM

clk = 01 hold transparent Q

Master-Slave Implementation
Master Slave

I2 T2 I3 I5 T4 I6 Q
QM

I1 T1 I4 T3
D

clk

master transparent master hold

slave hold slave transparent
clk

!clk
MS Timing Properties

 Assume propagation delays are tpd_inv and tpd_tx, that

the contamination delay is 0, and that the inverter
delay to derive !clk is 0
 Set-up time - time before rising edge of clk that D
must be valid
tsu = 3 * tpd_inv + tpd_tx

 Propagation delay - time for QM to reach Q

tc-q = tpd_inv + tpd_tx

 Hold time - time D must be stable after rising edge of

clk
thold = zero
Set-up Time Simulation

3
Q
2.5

2 tsu = 0.21 ns
QM
1.5 tsetup
Volts

1 D clk
0.5
I2 out
0

-0.5 works correctly

0 0.2 0.4 0.6 0.8 1
Time (ns)
Set-up Time Simulation

3
Q
2.5
I2 out tsu = 0.20 ns
2

1.5 tsetup
Volts

1 D clk
0.5
QM
0

-0.5 fails
0 0.2 0.4 0.6 0.8 1
Time (ns)
Propagation Delay Simulation

2.5

2 tc-q(LH) = 160 psec

1.5
Volts

1 tc-q(LH) tc-q(HL) = 180 psec

tc-q(HL)
0.5

-0.5
0 0.5 1 1.5 2 2.5
Time (ns)
Reduced Load MS FF
 Clock load per register is important since it directly
impacts the power dissipation of the clock network
 Can reduce the clock load (at the cost of robustness) by
making the circuit ratioed

clk !clk
I1 I3
QM
D T1 T2 Q

I2 I4
!clk clk
reverse conduction

 to switch the state of the master, T1 must be sized to overpower I2

 to avoid reverse conduction, I4 must be weaker
Non-Ideal Clocks

clk clk

!clk !clk

Ideal clocks Non-ideal clocks

clock skew

1-1 overlap

0-0 overlap
Example of Clock Skew Problems
X !clk Q
clk

P1 A P3 I3 I4 !Q
D I1 I2

B
P2 P4

!clk clk

Race condition – direct path from D to Q during the short

time when both clk and !clk are high (1-1 overlap)
Undefined state – both B and D are driving A when clk and
!clk are both high
Dynamic storage – when clk and !clk are both low (0-0
overlap)
Pseudostatic Two-Phase FF
X clk2 Q
clk1

P1 A P3 I3 I4 !Q
D I1 I2

B
P2 P4

clk2 clk1
dynamic
master transparent storage
slave hold

clk1 master hold

tnon_overlap slave transparent
clk2
Two Phase Clock Generator
A
clk1

clk B

clk2

clk1

clk2
Ratioed CMOS Clocked SR Latch

off  on on  off
M2 M4
Q 1 0
1 0 !Q
off on off on
0  1 clk M6 M8 clk 0  1
M1 M3
on  off off  on
M7 R1
0 S M5
off on
Sizing Issues

1.5
so W/L5and6 > 3
!Q (Volts)

0.5

0
2 2.5 3 3.5 4
W/L5and6
W/L2and4 = 1.5m/0.25 m
W/L1and3 = 0.5m/0.25 m
6 Transistor CMOS SR Latch

clk clk

R S

clk
clk M2 M4
Q M6 S
M5 !Q
R

M1 M3