Structure of a Typical Digital System

Execution Unit (Datapath)

• Provides All Necessary Resources

and Interconnects Among Them to
Perform Specified Task
• Examples of Resources
– Adders, Multipliers, Registers,
Memories, etc.
 Control Unit (Control)

• Controls Data Movements in an

Operational Circuit by Switching
Multiplexers and Enabling or Disabling
Resources
• Follows Some ‘Program’ or Schedule
• Often Implemented as Finite State
Machine or collection of Finite State
Machines
 FSMs in VHDL
• Finite State Machines Can Be Easily
Described With Processes
– State transitions should be described in a
process sensitive to clock and asynchronous
reset signals only
– Outputs described as concurrent statements
outside the process
Moore FSM
Mealy FSM
 Controller Description
• Sequence Detector
– Detection sequence is 110
x IF 110 found on x
Then Z gets ‘1’ z
Else z gets ‘0’
clk End

1 1 1 0
0
S0 S1 S2 S3
/0 /0 /0 /1

0 1

0
 VHDL Description of Moore 110 Sequence
Detector
ENTITY moore_110_detector IS
PORT (x, clk : IN BIT; z : OUT BIT);
END moore_110_detector;
ARCHITECTURE behavioral OF moore_110_detector IS
TYPE state IS (S0,S1,S2,S3);
SIGNAL current : state := S0;
BEGIN
PROCESS(clk)
BEGIN
IF (clk = '1' AND CLK’Event) THEN
CASE current IS
WHEN S0=>
IF x = '1' THEN current <= S1;
ELSE current <= S0; END IF;
WHEN S1 =>
IF x = '1' THEN current <= S2;
ELSE current <= S0; END IF;
WHEN S2=>
IF x = '1' THEN current <= S2;
ELSE current <= S3; END IF;
WHEN S3=>
IF x = '1' THEN current <=S1;
ELSE current <= S0; END IF;
END CASE;
END IF;
END PROCESS;
z <='1' WHEN current = S3 ELSE '0';
END behavioral;
 Moore FSM - Example
• Moore FSM that Recognizes Sequence
“10”

S0: No
elements S2: “10”
Meaning of the S1: “1” observed
of states: sequence observed
observed
 Moore FSM in VHDL
TYPE state IS (S0, S1, S2);
SIGNAL M_state: state;

U_Moore: PROCESS (clock, reset)

BEGIN
IF(reset = ‘1’) THEN
M_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE M_state IS
WHEN S0 =>
IF input = ‘1’ THEN
M_state <= S1;
ELSE
M_state <= S0;
END IF;
WHEN S1 =>
IF input = ‘0’ THEN
M_state <= S2;
ELSE
M_state <= S1;
END IF;
WHEN S2 =>
IF input = ‘0’ THEN
M_state <= S0;
ELSE
M_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN M_state = S2 ELSE ‘0’;
 Mealy FSM - Example
• Mealy FSM that Recognizes Sequence
“10”
 Mealy FSM in VHDL
TYPE state IS (S0, S1);
SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset, input)
BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
Mealy_state <= S0;
END IF;
WHEN S1 =>
IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
“Add and shift” binary multiplication
 Unsigned Binary Multiplier
Sequence of event
Initial content of the product register 000001011 M(11)
(add multiplicand since M=1) 1101 (13)
After addition 011011011
After shift 001101101 M
(add multiplicand since M=1) 1101
After addition 100111101
After shift 010011110 M
(skip addition since M=0)
After shift 001001111 M
(add multiplicand since M=1) 1101
After addition 100011111
after shift (final answer) 010001111
“Add and shift” multiply algorithm
(Moore model)
Example: 6 x 5 = 110 x 101
 Unsigned Binary Multiplier
product
ACC
load
Sh
Ad 8 7 6 5 4 3 2 1 0

CONTROL
UNIT Done
Clk
St
4-BIT ADDER
M
multiplier

Multiplicand
State diagram of multiplier
St’/0

done
St/Load
S0
-/Sh S9
S1
S8
M/Ad
M/Ad
M’/Sh
M’/Sh S2
S7
-/Sh
-/Sh M’/Sh

M’/Sh
S6 S3

M/Ad S5 M/Ad
S4
-/Sh
 VHDL Code
---maximum numbers of clock cycle needed is 10
library BITLIB; when 1 | 3 | 5 | 7 => --add /shift state
use BITLIB.bit_pack.all; if M = ‘1’ then
entity MULT4X4 is acc(8 downto 4) <= Add4(acc( 7 downto 4), Mcand, ‘0’);
port (clk, St: in bit; state <= State +1;
Mplier,Mcand: in bit_vector (3 downto 0); else
Done: out bit; acc<= ‘0’ & acc(8 downto 1);
Mout: out bit_vector (7 downto 0)); state <= State +2;
end mult4X4; end if;
architecture algoMult of mult4X4 is when 2 | 4 | 6 | 8 => -- shift state
signal state: integer range 0 to 9; acc<= ‘0’ & acc(8 downto 1); --right shift
signal acc: bit_vector(8 downto 0); state <= State +1;
alias M: bit is acc(0); -- LSB of acc when 9 =>
state <= 0;
Begin end case;
process end process;
begin Done <= ‘1’ when state = 9 else ‘0’;
wait until clk = ‘1’; Mout <= Acc;
case state is end algoMult;
when 0 =>
if St = ‘1’ then
acc(8 downto 4) <= “00000”;
acc(3 downto 0) <= Mplier;
state <= ‘1’
end if;
Flow Chart for Unsigned
8 Bit Multiplier Controller
START

C, A  0
M  Multiplicand
Q Multiplier
Count  0

No Yes
Q0 = 1? C, A A + M

Shift C,A,Q
Count Count + 1

No Yes
Count = n?

END
State Diagram for Unsigned 8 Bit
Multiplier Controller

Idle

START=‘1’

Initialize
Count=0

COUNT=n

Test
COUNT<n && Q0=‘0’ COUNT<n && Q0=‘1’

Shift
Count= Add
Count+1
 Unsigned 8 Bit Multiplier Control Unit
Behavioral Description
• Synthesizable VHDL state machine description
• Two internal state variables
– present_state
– present_count
• Three interacting VHDL processes
– Clock (or register) process
– State Transition process
– Output process
• Moore machine
• Asynchronous reset signal and synchronous
start signal
 Unsigned 8 Bit Multiplier Control Unit
(Entity)
LIBRARY gate_lib;
USE gate_lib.resources.all;
ENTITY mult_controller_behav IS
PORT(reset : IN level; -- global reset signal
start : IN level; -- input to indicate start of
process
q0 : IN level; -- q0 ,input from data path
clk : IN level; -- clock signal
a_enable : OUT level; -- clock enable for A register
a_reset : OUT level; -- Reset control for A register
a_mode : OUT level; -- Shift or load mode for A
c_enable : OUT level; -- clock enable for c register
m_enable : OUT level; -- clock enable for M register
q_enable : OUT level; -- clock enable for Q register
q_mode : OUT level); -- Shift or load mode for Q
END mult_controller_behav;

Data Path
Control
Mn-1
Multiplicand
M0
Unit

n-Bit Adder

Multiplier
C An-1 A0 Qn-1 Q0

Product
Unsigned 8 Bit Multiplier Control Unit
(Architecture - Clock Process)
ARCHITECTURE state_machine OF mult_controller_behav IS

SUBTYPE count_integer IS INTEGER RANGE 0 TO 8;

TYPE states IS (idle,initialize,test,shift,add);
SIGNAL present_state : states := idle;
SIGNAL next_state : states := idle;
SIGNAL present_count : count_integer := 0;
SIGNAL next_count : count_integer := 0;

BEGIN

CLKD : PROCESS(clk,reset)
BEGIN
IF(reset = '1') THEN
present_state <= idle;
present_count <= 0;
ELSIF(clk'EVENT AND clk = '1' AND
clk'LAST_VALUE = '0') THEN
present_state <= next_state;
present_count <= next_count;
END IF;
END PROCESS CLKD;
 Unsigned 8 Bit Multiplier Control Unit
(Architecture - State Transition Process)
STATE_TRANS : PROCESS(present_state,present_count,start,q0) WHEN add =>
BEGIN next_state <= shift;
next_state <= present_state; -- default case next_count <= present_count;
next_count <= present_count; -- default case WHEN shift =>
CASE present_state IS next_state <= test;
WHEN idle => next_count <= present_count +
IF(start = '1') THEN 1;
next_state <= initialize; WHEN OTHERS =>
ELSE next_state <= idle;
next_state <= idle; next_count <= present_count;
END IF; END CASE;
next_count <= present_count; END PROCESS STATE_TRANS;
WHEN initialize =>
next_state <= test;
next_count <= present_count;
WHEN test =>
IF(present_count < 8) THEN
IF(q0 = '0') THEN
next_state <= shift;
ELSE
next_state <= add;
END IF;
ELSE
next_state <= idle;
END IF;
next_count <= present_count;
 Unsigned 8 Bit Multiplier Control Unit
(Architecture - Output Process)
OUTPUT : PROCESS(present_state)
BEGIN
CASE present_state IS
WHEN idle =>
a_enable <= '0'; WHEN add =>
a_reset <= '1'; a_enable <= '1';
a_mode <= '1'; a_reset <= '1';
c_enable <= '0'; a_mode <= '1';
c_enable <= '1';
m_enable <= '0'; m_enable <= '0';
q_enable <= '0'; q_enable <= '0';
q_mode <= '1'; q_mode <= '0';
WHEN shift =>
WHEN initialize => a_enable <= '1';
a_enable <= '1'; a_reset <= '1';
a_reset <= '0'; a_mode <= '0';
c_enable <= '0';
a_mode <= '1'; m_enable <= '0';
c_enable <= '0'; q_enable <= '1';
m_enable <= '1'; q_mode <= '0';
WHEN OTHERS =>
q_enable <= '1'; a_enable <= '0';
q_mode <= '1'; a_reset <= '1';
WHEN test => a_mode <= '1';
c_enable <= '0';
a_enable <= '0'; m_enable <= '0';
a_reset <= '1'; q_enable <= '0';
a_mode <= '1'; q_mode <= '1';
END CASE;
c_enable <= '0'; END PROCESS OUTPUT;
m_enable <= '0';
q_enable <= '0'; END state_machine;
q_mode <= '1';
 Structural Test Bench
• A Testbench is an Entity without
Ports that has a Structural
Architecture
• The Testbench Architecture, in
general, has 3 major components:
– Instance of the Entity Under
Test (EUT)
– Test Pattern Generator (
Generates Test Inputs for the
Input Ports of the EUT)
– Response Evaluator
(Compares the EUT Output
Signals to the Expected
Correct Output)
 Testbench Example …
Entity nibble_comparator_test_bench IS
End nibble_comparator_test_bench ;
--
ARCHITECTURE input_output OF nibble_comparator_test_bench IS
--
COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0);
gt, eq, lt : IN BIT;
a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
--
FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative);
--
SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);
SIGNAL eql, lss, gtr, gnd : BIT;
SIGNAL vdd : BIT := '1';
--
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
--
 …Testbench Example
a2: a <= "0000", -- a = b (steady state)
"1111" AFTER 0500 NS, -- a > b (worst case)
"1110" AFTER 1500 NS, -- a < b (worst case)
"1110" AFTER 2500 NS, -- a > b (need bit 1 info)
"1010" AFTER 3500 NS, -- a < b (need bit 2 info)
"0000" AFTER 4000 NS, -- a < b (steady state, prepare FOR next)
"1111" AFTER 4500 NS, -- a = b (worst case)
"0000" AFTER 5000 NS, -- a < b (need bit 3 only, best case)
"0000" AFTER 5500 NS, -- a = b (worst case)
"1111" AFTER 6000 NS; -- a > b (need bit 3 only, best case)
--
a3 : b <= "0000", -- a = b (steady state)
"1110" AFTER 0500 NS, -- a > b (worst case)
"1111" AFTER 1500 NS, -- a < b (worst case)
"1100" AFTER 2500 NS, -- a > b (need bit 1 info)
"1100" AFTER 3500 NS, -- a < b (need bit 2 info)
"1101" AFTER 4000 NS, -- a < b (steady state, prepare FOR next)
"1111" AFTER 4500 NS, -- a = b (worst case)
"1110" AFTER 5000 NS, -- a < b (need bit 3 only, best case)
"0000" AFTER 5500 NS, -- a = b (worst case)
“0111" AFTER 6000 NS; -- a > b (need bit 3 only, best case)
END input_output;