SMART ATTENDANCE

SYSTEM USING FPGA

Guided by,
Dr. K Sivasankaran
Associate Professor Debolina Roy 19MVD0024

Department of Micro and Nanoelectronics Athira Shanker 19MVD0033

Mebin PM 19MVD0044
School of Electronics Engineering
OBJECTIVE

❖ To design a smart attendance system using FPGA

❖ To implement face detection algorithms in FPGA
❖ To implement face recognition algorithm in FPGA.
❖ To design a FPGA based hardware logic circuit.
❖ To evaluate the performance of the system.
LITERATURE SURVEY
➢ Viola-Jones Algorithm
Viola- Jones algorithm which consists of an Adaboost algorithm and Haar feature
classifiers.

A. Alahmadi and S. M. Qaisar, “Robust Real-time Embedded Face Detection Using Field
Programmable Gate Arrays (FPGA),” 2019 Advances in Science and Engineering
Technology International Conferences (ASET), 2019
➢ LBP(Local Binary Pattern) generation and AdaBoost algorithm
Combines the LBP generation and AdaBoost based Haar classifier.Requires large size of
classifier logic and internal memory size.

Sang-Seol Lee, Sung-Joon Jang, Jungho Kim and Byeongho Choi, “A Hardware
Architecture of Face Detection for Human-robot Interaction and its Implementation”, 2016
IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)
➢ Background Subtraction Algorithm
Needs adaptive threshold value for each input video frame where pixel range varies from 10
to 85.Overcomes the problem of less accuracy when subtracting pixel values of background
video from input video.

Vidya, Mohana, H. V. Ravish Aradhya, “An Area Efficient FPGA Implementation of Moving
Object Detection and Face Detection using Adaptive Threshold Method”, 2nd IEEE
International Conference On Recent Trends in Electronics Information & Communication
Technology (RTEICT), May 19-20, 2017,
➢ Principal Component Analysis(PCA)
Processes the data with Eigenfaces. Features extracted and stored as
eigenvectors.

L. Schaffer, Z. Kincses, and S. Pletl, “FPGA-based low-cost real-time face recognition,” 2017
IEEE 15th International Symposium on Intelligent Systems and Informatics (SISY), 2017.
➢ Linear Discriminant Analysis
Similar to PCA, Reduces in class scatter and increases between class scatter.

S. Poornima, N. Sripriya, B. Vijayalakshmi, and P. Vishnupriya, “Attendance monitoring

system using facial recognition with audio output and gender classification,” 2017
International Conference on Computer, Communication and Signal Processing (ICCCSP),
2017.
DISCRETE WAVE TRANSFORM (DWT)

Coefficient selection for DWT used for face recognition.Aims in transforming input images into
wavelet coefficients by FPGA based intellectual property core implementation.

Afandi Ahmad , Abbes Amira , Paul Nicholl and Benjamin Krill,”FPGA-based IP cores
implementation for facerecognition using dynamic partial reconfiguration,”Published in
Journal of Real-Time Image Processing Volume 8 Issue 3, September 2013.
METHODOLOGY

● Methodologies which need to be processed in following

steps:
○ Creating face database
image face detect face extract creating a dbms folder with list of
subjects.
○ Realtime video recording
○ Face detection
○ Face recognition
○ Registering attendance
BLOCK DIAGRAM
Camera

Face Detection
(Viola Jones algorithm)

Image Face Recognition Attendance

Database (PCA algorithm) Server

Stop
Face Detection using Viola Jones Algorithm

➢ Initially a set of Haar Features are selected, like, eyes,

eyebrows, nose.
➢ Then integral image is generated.
○ The integral image allows integrals for the Haar extractors
to be calculated by adding only four numbers.
➢ Single Haar-like feature has weak discrimination capability.
Therefore Adaboost algorithm required.
➢ A set of cascade classifiers are used to detect a face window
and discard a non face window.
Face Detection using Viola Jones Algorithm

Input Cascade Output

Haar Feature AdaBoost
Integral Image Classifier
Selection Training
Face recognition using Principal Component
Analysis (PCA)
1. Creating a training set and loading it with M face images.
2. Converting the face images in the training set to face vectors.
3. Normalizing the face vectors i.e removing the common features that these faces share together.
4. Decomposition of covariance matrix for calculation of eigen vectors.
5. Dimension reduction to reduce calculation and effect of noise.
6. Converting the lower dimension vectors from the reduced dimension set to original face
dimensionality.
7. Each face of the training set can be represented as a weighted sum of K eigen vectors + mean face
image
HARDWARE DESIGN BLOCK DIAGRAM

Intel FPGA Cyclone IV

Capture &
Camera Control RAM VGA VGA
Module Logic Driver Display

Face Face
Detection Recognition Attendance
Logic Logic Server
Clock
Generator
IMPLEMENTATION

 MATLAB implementation of Face detection.

 Implementation of video capture and display using platform designer tool
in Quartus.
 Verilog implementation of gray scale conversion was done by first
converting bitmap (.bmp) image into hexadecimal (.hex) format.
RESULTS
● Matlab implementation of viola jones algorithm for face detection.
HARDWARE SETUP FOR VIDEO CAPTURE AND DISPLAY
CAPTURED VIDEO ON VGA MONITOR
RGB IMAGE READ FROM SPECIFIED MEMORY
LOCATION
OUTPUT IMAGE AFTER GRAYSCALE
CONVERSION
DISCUSSIONS

❖ Literature survey done.

❖ Understandings of the algorithm
▪ Face detection- Viola Jones
▪ Face Recognition – PCA
❖ MATLAB Implementation of Face Detection.
❖ Intended to implement face detection.
REFERENCES

1. Alahmadi and S. M. Qaisar, “Robust Real-time Embedded Face Detection Using Field Programmable Gate
Arrays (FPGA),” 2019 Advances in Science and Engineering Technology International Conferences (ASET),
2019.
2. S. V. Chakrasali and S. Kuthale, “Optimized face detection on FPGA,” 2016 International Conference
on Circuits, Controls, Communications and Computing (I4C), 2016.

3. Raghuwanshi and P. D. Swami, “An automated classroom attendance system using video based
face recognition,” 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information &
Communication Technology (RTEICT), 2017.
[4.] S. Poornima, N. Sripriya, B. Vijayalakshmi, and P. Vishnupriya, “Attendance monitoring system using
facial recognition with audio output and gender classification,” 2017 International Conference on
Computer, Communication and Signal Processing (ICCCSP), 2017
[5.] L. Schaffer, Z. Kincses, and S. Pletl, “FPGA-based low-cost real-time face recognition,” 2017 IEEE
15th International Symposium on Intelligent Systems and Informatics (SISY), 2017.
[6.]V. P. Korakoppa, Mohana, and H. V. R. Aradhya, “An area efficient FPGA implementation of moving
object detection and face detection using adaptive threshold method,” 2017 2nd IEEE International
Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), 2017.
[7] Ahmad, A. Amira, P. Nicholl, and B. Krill, “FPGA-based IP cores implementation for face recognition
using dynamic partial reconfiguration,” Journal of Real-Time Image Processing, vol. 8, no. 3, pp. 327–
340, 2011.
[8] D. N. Arya, S. K.l.v., R. Reddy, S. S, and S. K, “A face detection system implemented on FPGA
based on RCT colour segmentation,” 2016 Online International Conference on Green Engineering and
Technologies (IC-GET), 2016.
[9] Liton Chandra Paul, Abdulla Al Sumam, “Face Recognition Using Principal Component Analysis
Method,”International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 1, Issue 9, November.
[10] N. Çevik and T. Çevik, “A novel high-performance holistic descriptor for face retrieval,” Pattern
Analysis and Applications, 2019