What is RTL Design:

This is the method currently used for the design of complex

logic circuits such as microprocessors .
 Terms
• Synthesis:
- Synthesis is a process of creating a gate level
description of the blocks that are described
behaviourally in verilog/ VHDL and preparing the
complete design for place and route.
- It is a process of converting RTL (Synthesizable
verilog code) to technology specific gate level
netlist (includes nets, sequential, and
combinational cells) and their connectivity.
• Verification: checking whether the synthesis
steps has satisfies the design constaints.
• Optimization: Increasing the quality of the
design by rearrangements in a given
description (eg; Logic optimizer, timing
optimizer)
• Analysis/ testing: Collecting information on
the quality of the design. ( Area, timing and
power analysis).