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DC BIASING - BJT - Fixed - Bias
DC BIASING - BJT - Fixed - Bias
I E IC I B
IC
IB
I E ( 1)I B I C
V CB V CE V BE
V CB V CE V BE
Operating Point
Limited to The device can
𝑉𝐶𝐸 = 0 and react to both
𝐼𝐶 = 0 positive and
negative input
signal
The device
operating near max
voltage and power
No bias
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Operation Region
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• BJT need to be operate in active region used
as amplifier.
• The cutoff and saturation region used as a
switches.
• For the BJTs to be biased in its linear or active
operating region the following must be true:
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DC Biasing Circuits
• Fixed-bias circuit
• Emitter-stabilized bias circuit
• Collector-emitter loop
• Voltage divider bias circuit
• DC bias with voltage feedback
Fixed Bias Configuration
• The configuration:
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Fixed Bias Configuration
The network can be isolated from the
indicated ac levels by replacing the capacitors
with an open-circuitequivalent [ the reactance
of a capacitor for dc is ∞Ω]
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Fixed Bias Configuration 2 loops
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Fixed Bias Configuration
DC equivalent circuit:
1. BE loop
−𝑉𝐶𝐶 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 = 0
Write KVL equation 𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
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Fixed Bias Configuration
DC equivalent circuit: 𝐼𝐶 = 𝛽𝐼𝐵
2. CE loop
−𝑉𝐶𝐶 + 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 = 0
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
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Fixed Bias Configuration
DC equivalent circuit:
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
𝐼𝐶 = 𝛽𝐼𝐵
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
Find 𝑉𝐵 , 𝑉𝐶 , and 𝑉𝐸
𝑉𝐵𝐸 = 𝑉𝐵 − 𝑉𝐸
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Fixed Bias Configuration
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Transistor Saturation
• “Saturation”: reached their maximum value.
• In transistor, saturation region is where the
current is in maximum value for the particular
design.
• Normally avoided:
– The BC junction is no longer reverse-biased
– As a result, the output amplified signal will be distorted.
[𝑉 , 𝑉 ]
𝐶𝐸 𝐶𝐵
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Transistor Saturation
Actual Approximate
𝑉𝐶𝐸 = 0,
𝐼𝐶 = 𝐼𝐶𝑠𝑎𝑡
𝑉𝐶𝐸 = 0
Notice that in saturation region, 𝑉𝐶𝐸 = 0
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Saturation Level
For the fixed-bias configuration, to determine the
saturation current, 𝐼𝐶 𝑠𝑎𝑡 , the equivalent circuit is:
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
𝑉𝐶𝐸 = 0 𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
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Transistor Saturation
• “Saturation”: reached their maximum value.
• In transistor, saturation region is where the
current is in maximum value for the particular
design.
• Normally avoided:
– The BC junction is no longer reverse-biased
– As a result, the output amplified signal will be distorted.
[𝑉 , 𝑉 ]
𝐶𝐸 𝐶𝐵
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Transistor Saturation
Actual Approximate
𝑉𝐶𝐸 = 0,
𝐼𝐶 = 𝐼𝐶𝑠𝑎𝑡
𝑉𝐶𝐸 = 0
Notice that in saturation region, 𝑉𝐶𝐸 = 0
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Load Line Analysis
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Load Line Analysis
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Load Line Analysis
How
Step 1:toFind
plot load
𝐼𝐶max line:
when 𝑉𝐶𝐸 = 0
From 𝑉𝐶𝐸 = 𝑉𝐶𝐶 – 𝐼𝐶 𝑅𝐶 ,
and 𝑉𝐶𝐸 = 0
𝑉𝐶𝐶
𝐼𝐶 =
𝑅𝐶
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Load Line Analysis
How
Step 2:toFind
plot
𝑉𝐶𝐸load
max
line:𝐼𝐶
when = 0
From 𝑉𝐶𝐸 = 𝑉𝐶𝐶 – 𝐼𝐶 𝑅𝐶 ,
and 𝐼𝐶 = 0
𝑉𝐶𝐸 = 𝑉𝐶𝐶
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Load Line Analysis
𝑉𝐶𝐶
How to plot load line: 𝐼𝐶 =
𝑅𝐶
𝑉𝐶𝐸 = 𝑉𝐶𝐶
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Load Line Analysis
The characteristic becomes:
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Load-Line Analysis
The characteristic becomes:
𝑰𝑩 𝑹𝐂 𝑽𝑪𝑪
Increase or decrease of
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FIXED BIAS CIRCUIT
DISADVANTAGES
• Unstable – because it is too dependent on β
and produce width change of Q-point
• For improved bias stability , add emitter
resistor to dc bias.