CPU Organisation & Operation

Computer Architecture (K.K. Leung) CPU Organisation & Operation (1)

CPU Organisation
CPU R0 000
R1 Address 001
Bus 002
R2 I 003
R3 n
t
ALU e
Input Reg1 Data
r Bus
Output Reg RAM
n
Input Reg2 a
l
Control
Program Counter B Bus
u
Instr. Decoder Instr. Register s
3FD
3FE
Control Unit 3FF

Computer Architecture (K.K. Leung) CPU Organisation & Operation (2)

LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

080H
080H
PC 080H 0
Instr. Decoder
3FD
0
0 3FE
Control Unit 3FF
1
Computer Architecture (K.K. Leung) CPU Organisation & Operation (3)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

PC 080H + 1 0
Instr. Decoder
3FD
3FE
Control Unit 3FF
2
Computer Architecture (K.K. Leung) CPU Organisation & Operation (4)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

0
PC 081H
Instr. Decoder
3FD
3FE
Control Unit 3FF
3
Computer Architecture (K.K. Leung) CPU Organisation & Operation (5)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H
R2
080 1A01H
1A01
081 3A02H
ALU 082 2A00H

RAM

200 0000
0 201 0009
PC 081H 202 0006

Instr. Decoder
3FD
3FE
Control Unit 3FF
4
Computer Architecture (K.K. Leung) CPU Organisation & Operation (6)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
201H
R2
080 1A01H
081 3A02H

201H
ALU 082 2A00H
1A01H 1A01
RAM

1A01H
200 0000
201 0009
PC 081H 0 202 0006
1A01H
1A01H 1A01H
3FD
0
1, 2, 201H 201H 3FE
1, 2, 201H 3FF
0 5
Computer Architecture (K.K. Leung) CPU Organisation & Operation (7)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
201H
0009 201H
R2 0009
080 1A01H
081 3A02H

0009
ALU 082 2A00H
0009 0009
RAM

200 0000
201 0009
0
PC 081H 0 202 0006

1A01H
3FD
3FE
1, 2, 201H 3FF
6
Computer Architecture (K.K. Leung) CPU Organisation & Operation (8)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
R2 0009
080 1A01H
081 3A02H

081H
ALU 082 2A00H

RAM

200 0000
201 0009
081H
PC 081H 0 202 0006

3FD
0 0 3FE
3FF
7
Computer Architecture (K.K. Leung) CPU Organisation & Operation (9)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
R2 0009
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 081H + 1 0 202 0006

3FD
3FE
3FF
8
Computer Architecture (K.K. Leung) CPU Organisation & Operation (10)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
0009 202H
R2 0009
0009

202H 0009
080 1A01H
081 3A02H
3A02
ALU 0009 082 2A00H
0009 3A02H 3A02H
RAM

3A02H
200 0000
201 0009
PC 082H 0 0 202 0006
3A02H
3A02H 3A02H
3FD
0
3, 2, 202H 202H 3FE
3, 2, 202H 3FF
0 9
Computer Architecture (K.K. Leung) CPU Organisation & Operation (11)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
000FH 202H 202H
R2 000FH
0009
080

000FH
1A01
081 3A02
ALU 082 2A00
0009 0006 0006
000FH ADD RAM

000FH
0006
000FH 0006
200 0000
201 0009
PC 082H 0 0 202 0006

3A02H
3FD
3FE
3, 2, 202H 3FF
10
Computer Architecture (K.K. Leung) CPU Organisation & Operation (12)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
082H
R2 000FH
080 1A01H
081 3A02H

082H
ALU 082 2A00H

RAM

200 0000
201 0009
082H
PC 082H 0 202 0006

3FD
0 0 3FE
3FF
11
Computer Architecture (K.K. Leung) CPU Organisation & Operation (13)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
082H
R2 000FH
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 082H + 1 0 202 0006

3FD
3FE
3FF
12
Computer Architecture (K.K. Leung) CPU Organisation & Operation (14)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
200H 082H
000FH
R2 000FH

200H 000FH
000F
080 1A01H
081 3A02H
ALU 082 2A00H
2A00
000FH 2A00H
RAM

2A00H
200 0000
201 0009
PC 083H 1 1 202 0006
2A00H
2A00H 2A00H
3FD
1
2, 2, 200H 200H 3FE
2, 2, 200H 3FF
1 13
Computer Architecture (K.K. Leung) CPU Organisation & Operation (15)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
200H 200H
R2 000FH
080 1A01H
081 3A02H
ALU 082 2A00H
00FH 00FH
RAM

200 000FH
0000
1 201 0009
1
PC 083H 202 0006

3FD
3FE
3FF
14
Computer Architecture (K.K. Leung) CPU Organisation & Operation (16)