Unit 1:

Environment and
Crystal Growth for
VLSI Technology
1.1 Environment: Semiconductor technology trend,
Clean rooms, Wafer cleaning
-Reference: James D. Plummer, Michael D. Deal and Peter
B. Griffin, “Silicon VLSI Technology”, Pearson, Indian Edition

1.2 Semiconductor Substrate: Phase diagram and

solid solubility, Crystal structure, Crystal defects,
Czochralski growth, Bridgman growth of GaAs, Float
Zone growth, Wafer Preparation and specifications
-Reference: Stephen A. Campbell, “The Science and
Engineering of Microelectronic Fabrication”, Oxford University
Press, 2nd Edition.
 1.1
Environment:
Semiconductor technology
trend, Clean rooms, Wafer
cleaning
 Electron Bands
• Electrons circle nucleus in
defined shells
– K 2 electrons L
– L 8 electrons
– M 18 electrons K
– N 32 electrons
• Within each shell, electrons
are further grouped into
subshells
– s 2 electrons
– p 6 electrons
– d 10 electrons
– f 14 electrons d
• electrons are assigned to shells p
and subshells from inside out s
– Si has 14 electrons: 2 K, 8 L, 4
M
 Semiconductor Crystalline Structure
• Semiconductors have a
regular crystalline structure

• Atoms occupy fixed positions

relative to one another, but
are in constant vibration
about equilibrium
 Semiconductor Crystalline Structure
• Silicon atoms have 4 electrons
in outer shell
– inner electrons are very
closely bound to atom
• These electrons are shared
with neighbor atoms on both
sides to “fill” the shell
– resulting structure is very
stable
– electrons are fairly tightly
bound
• no “loose” electrons
– at room temperature, if
battery applied, very little
electric current flows
Insulators, Semiconductors, and Metals
• Forbidden gap/Energy gap, separation of the
valence and conduction bands determines the
electrical properties of the material
• Insulators have a large energy gap
– electrons can’t jump from valence to conduction bands
– no current flows
• Conductors (metals) have a very small (or
nonexistent) energy gap
– electrons easily jump to conduction bands due to
thermal excitation
– current flows easily
• Semiconductors have a moderate energy gap
– only a few electrons can jump to the conduction band
• leaving “holes”
– only a little current can flow
 Insulators, Semiconductors, and
Metals (continued)

Conduction
Band

Valence
Band

Conductor Semiconductor Insulator

 Hole - Electron Pairs
• Sometimes thermal energy is enough to cause an electron
to jump from the valence band to the conduction band
– produces a hole - electron pair
• Electrons also “fall” back out of the conduction band into
the valence band, combining with a hole

pair elimination pair creation

hole electron
 Improving Conduction by Doping
• To make semiconductors better conductors,
add impurities (dopants) to contribute extra
electrons or extra holes
– elements with 5 outer electrons contribute an
extra electron to the lattice (donor dopant)
– elements with 3 outer electrons accept an
electron from the silicon (acceptor dopant)
 Improving Conduction by Doping
• Phosphorus and arsenic are
donor dopants
– if phosphorus is introduced
into the silicon lattice,
there is an extra electron
“free” to move around and
contribute to electric
current
• very loosely bound to atom
and can easily jump to
conduction band
– produces n type silicon
• sometimes use + symbol to
indicate heavier doping, so
n+ silicon
– phosphorus becomes
positive ion after giving up
electron
 Improving Conduction by Doping
• Boron has 3 electrons in
its outer shell, so it
contributes a hole if it
displaces a silicon atom
– boron is an acceptor
dopant
– yields p type silicon
– boron becomes negative
ion after accepting an
electron
 Semiconductor essentials

n-type doped semiconductor p-type doped semiconductor

e.g. silicon with phosphorus impurity e.g. silicon with Al impurity
electrons determine conductivity holes determine conductivity

p-n junction:
current can only flow one way!
Semiconductor diode
 Epitaxial Growth of Silicon
• Epitaxy refers to the deposition of a crystalline over layer on a
crystalline substrate. The overlayer is called an epitaxial film
or epitaxial layer. The term epitaxy comes from the Greek
roots epi meaning "above", and taxis meaning "an ordered
manner”
• Epitaxy grows silicon on top of existing silicon
– uses chemical vapor deposition
– new silicon has same crystal structure as original
• Silicon is placed in chamber at high temperature[1200oC
(2150 o F)]
• Appropriate gases are fed into the chamber
– other gases add impurities to the mix
• Can grow n type, then switch to p type very quickly.
Semiconductor economy
The first transistor
Kilby’s first IC Germanium
1.5 mm x 1 mm
Fairchild’s flip-flop 1961 :4 transistors, 5 resistors

1.5 mm
 RCA, 1962
Logic chip, 16 transistors
First MOSFET IC

RCA:
Radio Corporation of America

NIKHEF, July 4, 2003 Jurriaan Schmitz, University of Twente

 5
10
Gordon Moore 1965
Number of components per chip

Fairchild
4
10

3
10

2
Moore’s Law (1965)
10

Progress in technology:
1
10 At the same cost, one can add
more and more components on a
chip.
0
10 1960 1965 1970 1975 The number of components
Year doubles each 1.5 years.
 Impact of Moore’s Law
• Device dimensions shrink (scaling)
• Cost per function decreases (~ 35% per year)
• Power per function decreases
• Speed increases
• … application field of semiconductors increases!
(e.g. personal computers, handheld telephones, solid
state audio, speech recognition)
The FEATURE SIZE of any semiconductor technology is defined
as the minimum length of the MOS transistor channel
between the drain and the source, leads to faster transient
response of the transistors.
180nm -->> 130nm -->> 90nm -->> 65nm -->> 40nm -->> 28nm --> 22nm...

the numbers above from 180nm to 130nm to 90nm scale

down by roughly a factor of 0.7. What's so special about 0.7?
If the feature size of the transistor is scaled by 0.7, the area
would be scaled by a factor of 0.72=0.49 =~ 0.5. That means if
we scale our feature sizes by a factor of roughly 0.7, we would
be able to pack twice the number of transistors on the same
area as the previous technology!
 Transistor downscaling
• Reduction of gate length (lithography)
• Increase of impurity concentrations
• Decrease of gate dielectric
• Reduction of source and drain dimensions

Brews’ Law:
Lmin = 0.4 [ xj tox (Ws + Wd)2 ]1/3
• Lmin: minimum gate length with normal behaviour
• xj: source and drain depth
• tox: gate dielectric thickness
• Ws, Wd: depletion widths of source and drain junctions
Clean Rooms and
Wafer Cleaning
 Clean rooms
-Specially constructed, environmentally controlled
enclosed spaces with respect to airborne
particulates, temperature, humidity, air pressure,
airflow patterns, air motion, vibration, noise,
viable (living) organisms, and lighting.
-Federal Standard 209E (FS-209E) provides
Clean Room Classes.
“Federal Standard 209E” defines a clean room as
a room in which the concentration of airborne
particles is controlled to specified limits.
 Type of contaminants
Contaminants may consist of particles, organic films,
photoresist, heavy metals or alkali ions.

Particles
Na Cu

Photoresist
Fe Au

N, P
SiO2 or other thin films Interconnect Metal

Silicon Wafer

Modern IC factories employ a three tiered approach

to controlling unwanted impurities:
1. clean factories
2. wafer cleaning
3. gettering
27
Controlled Environments –
Types of Contaminants
•Non-viable Particulates
-Metal specks, fiber from clothing
-Obtained from: Equipment, people, tools
•Viable (micro-organisms)
-Bacteria
-Yeast, molds
-Obtained from: People, outside air, water,
equipment, tools, excipients, active
ingredients
Particle contaminants
Particle sources: air, people, equipment and
chemicals.
A typical person emits 5-10 million particles per
minute.
Particle density (number/ml)
for ULSI grade chemicals

>0.2m >0.5m
NH4OH 130-240 15-30

H2O2 20-100 5-20

HF 0-1 0

HCl 2-7 1-2

H2SO4 180-1150 10-80

ULSI: ultra-large-scale integration

29
 Metal contamination
Sources: chemicals, ion implantation, reactive ion etching, resist
removal, oxidation. Fe, Cu, Ni, Cr,
Effects: defects at interface degrade device; leads to leak current W, Ti…
of p-n junction, reduces minority carrier life time. Na, K, Li…

Ion
implantation

Dry etching

Photoresist
removal
Fe Ni Cu
Wet oxidation

9 10 11 12 13
Log (concentration/cm2)
30
Sources of contamination
Internal Sources-
-The potentially largest source is from people in the
clean room, plus shedding of surfaces, process
equipment and the process itself.
People in the workspace generate particles in the
form of skin flakes, lint, cosmetics, and respiratory
emissions.
-Industry generates particles from combustion
processes, chemical vapors, soldering fumes, and
cleaning agents.
- The size of these particles ranges from 0.001 to
several hundred microns.
 Clean factory is the first approach against contamination

Modern IC factories employ a three tiered approach

to controlling unwanted impurities:
1. clean factories
2. wafer cleaning
3. gettering

Clean factory Wafer cleaning Gettering

32
Control precautions include:
1. Walls, floors, ceiling tiles, lighting fixtures, doors, and
windows are construction materials that must be carefully
selected to meet clean room standards.
2. People must wear garments to minimize the release of
particles into the space. Socks, coveralls, gloves, and head and
shoe covers are clothing accessories commonly used in clean
spaces.
3. Materials and equipment must be cleaned before entering
the clean room.
4. Room entrances such as air locks and pass-through are
used to maintain pressure differentials and reduce
contaminants.
5. Air showers are used to remove contaminants from
personnel before entering the clean space.
External Sources –
-For any given space, there exists the external influence of
gross atmospheric contamination.
-External contamination is brought in primarily through the
air conditioning system through makeup air.
-Also, external contamination can infiltrate through building
doors, windows, cracks, and wall penetrations for pipes,
cables and ducts.

The external contamination is controlled primarily by

1. High efficiency filtration,
2. Space pressurization and
3. Sealing of space penetrations

Factory environment is cleaned
by:
• HEPA filters and recirculation
for the air.
• “Bunny suits” for workers.
• Filtration of chemicals and
gases.
• Manufacturing protocols.
Clean room
HEPA: High Efficiency Particulate Air
• HEPA filters composed of thin porous sheets of
ultrafine glass fibers (<1m diameter).
• It is 99.97% efficient at removing particles from air.
• Room air forced through the filter at 50cm/sec.
• Large particles trapped, small ones stick to the fibers
due to electrostatic forces.
• The exit air is typically better than class 1.
35
 FILTRATION
Most filters are defined by their particle removal efficiency and airflow
rate.
Clean room air filtration technology centers around two types:
• High efficiency particulate air (HEPA):
-replaceable
-Extended media dry-type having a minimum particle collective
efficiency of 99.97 to 99.997%
- efficient for particles sizes of a 0.3 micron particle
-0.3 micron is 1/75,000 of an inch or 1/300, the diameter of the
human hair.

• Ultra low penetration air (ULPA):

-replaceable
extended media dry filters that have a minimum particle collection
efficiency of 99.9997 %
-efficient for particles greater than or equal to 0.12-micron in size.
 Application Guidelines
•The industry differentiates between the cleanliness of rooms by
referring to class numbers.
•Federal Standard 209E, categorize clean rooms in six general classes,
depending on the particle count (particles per cubic foot) and size in
microns (µm). The first three classes allow no particles exceeding 0.5
microns (µm), and the last three allowing some particles up to 5.0
microns.

•Eg.: a class 100,000

clean room limits the
concentration of
airborne
particles equal to or
greater than 0.5
microns to 1 00,000
particles in a cubic
foot of air.
 Clean Rooms - Semiconductor Manufacturing
-The production of microelectronic semiconductor products
requires a facility that is environmentally controlled and
virtually free from contaminants.
-A deposited particle having a diameter of 10% of the circuit is
likely to result in a circuit failure.
-With circuit line widths of 0.25 microns, particles of 0.025
microns are a concern.
Common design practices in existing facilities:
1) The facility is segregated to various class levels according to
requisite needs. For example, the uncrating of incoming items
may be Class 100,000, the next stage of setup and inspection
is Class 10,000 area and the final stage before entering the
main area is Class 1000.
2) In semiconductor clean rooms, the air stream sometimes
contains acid, solvent, toxic fumes, and process heat, and
therefore requires careful consideration of the material used
in the ducts. The fiberglass reinforced plastic (FRP) ducts are
sometimes used for corrosive fume exhaust systems.
3) The major internal load components are people, process
equipment and fan energy. Because clean rooms are usually
located within conditioned spaces, traditional infiltration,
solar and heat conduction losses is minimal (less than 2 to 3%
of the total load).
 Modern wafer cleaning
• Cleaning involves removing particles, organics and metals from wafer surfaces.
• Particles are largely removed by ultrasonic agitation during cleaning.
• Organics (photoresist) are removed in O2 plasma or in H2SO4/H2O2 (Piranha) solutions.
• The “RCA clean” is used to remove metals and any remaining organics.

A cassette of wafers

Typical person emit 5-10

million particle per
minute.
Most modern IC plants
use robots for wafer
handling.
41
 Standard RCA H2SO4/H2O2
1:1 to 4:1
120 - 150ÞC
10 min
Strips organics
especially photoresist
cleaning procedure
HF/H2O Room T Strips chemical
RCA clean is “standard 1:10 to 1:50 1 min oxide
process” used to remove and all contaminants on
top of it, but induces H
organics, heavy metals and passivated surface (bad)
alkali ions. DI H2O Rinse Room T

Ultrasonic agitation is used

to dislodge particles. NH4OH/H 2O2/H2O 80 - 90ÞC Strips organics,
SC: Standard Cleaning 1:1:5 to 0.05:1:5 10 min metals and particles
SC-1 Less NH4OH will reduce
RCA: Radio Corporation of surface roughness
America, now makes TV,
stereos… DI H2O Rinse Room T

HCl/H2O2/H2O
80 - 90ÞC Strips alkali ions
1:1:6 10 min and metals
SC-2 not removed by SC-1

DI water: de-ionized water HF dip added to remove oxide

DI H2O Rinse Room T 42
 Wafer cleaning
-Wafer cleaning is based on hot alkaline and acidic hydrogen
peroxide solutions, a process known as "RCA Standard Clean.“
-The RCA clean is a standard set of wafer cleaning steps which
need to be performed before high-temperature processing
steps (oxidation, diffusion, CVD) of silicon wafers in
semiconductor manufacturing.
-It involves the following chemical processes performed in
sequence:
Removal of the organic contaminants (organic clean +
particle clean)
Removal of thin oxide layer (oxide strip, optional)
Removal of ionic contamination (ionic clean)
First step (SC-1): organic clean + particle clean
Also called SC-1, (SC stands for Standard Clean) is
performed with a solution of
•5 parts of deionized water
•1 part of aqueous NH4OH (ammonium hydroxide)
•1 part of aqueous H2O2 (hydrogen peroxide)
at 75 or 80 °C typically for 10 minutes.
-This base-peroxide mixture removes organic residues and
also Particles are removed very effectively ,even insoluble
particles, and causes them to repel.
-This treatment results in the formation of a thin silicon
dioxide layer (about 10 Angstrom) on the silicon surface,
along with a certain degree of metallic contamination
(notably Iron) that shall be removed in subsequent steps.
Second step (optional): oxide strip
-second step (for bare silicon wafers) is a short immersion in a
1:100 or 1:50 solution of HF + H2O at 25 °C for about fifteen
seconds, in order to remove the thin oxide layer and some fraction
of ionic contaminants.
-If this step is performed without ultra high purity materials, it can
lead to recontamination since the bare silicon surface is very
reactive.
Third step (SC-2): ionic clean
Also called SC-2, is performed with a solution of
5 parts of deionized water
1 part of aqueous HCl (hydrochloric acid)
1 part of aqueous H2O2 (hydrogen peroxide)
at 75 or 80 °C, typically for 10 minutes.
-effectively removes the remaining traces of metallic (ionic)
contaminants,
- It also leaves a thin passivating layer on the wafer surface, which
protects the surface from subsequent contamination
Fourth step: rinsing and drying
-Provided the RCA clean is performed with high-purity
chemicals and clean glassware, it results in a very clean wafer
surface while the wafer is still submersed in water.
-Rinsing after wet cleaning is done with flowing high purity
and ultra filtered high-resistivity DI water (De-Ionized Water
free from all charged atoms or molecules (ions)), usually at
room temperature.
-Wafer drying after rinsing must be done by physical removal
of the water rather than by allowing it to evaporate.

In short, RCA cleaning (also known as SC1/SC2 etching)

submits silicon wafers to oxidation by NH3:H2O2:H2O
mixtures, oxide removal in diluted HF, further oxidation by
HCl:H2O2:H2O mixtures, and final etching in diluted HF.