Digital Integrated Circuits

Design

Instructor: Sheetal Bhandari

Slide Sources:
Rabaey, chandrakasan and Nikolic book website
(copyright Pearson)adapted

Devices
Sizing Inverter chain

Devices
Inverter Chain

In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

Devices
Inverter Delay
• Minimum length devices, L=0.25m
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays W
• Analyze as an RC network
1 1
 WP   WN 
RP  Runit    Runit    RN  RW
 Wunit   Wunit 

Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL

W
Load for the next stage: C gin 3 Cunit
Wunit
Devices
Inverter with Load
Delay

RW

CL
RW Load (CL)
tp = k RWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
Devices
 Inverter with Load
CP = 2Cunit Delay

2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

Devices
Delay Formula

Delay ~ RW  Cint  C L 

t p  kRW Cint 1  C L / Cint   t p 0 1  f /  

Cint = Cgin with   1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
Devices
Apply to Inverter Chain
In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C gin, j 1 
t pj ~ Runit Cunit 1  
 C 
 gin , j 
N N  C gin, j 1 
t p   t p , j  t p 0  1  , C gin, N 1  C L
 C
i 1 

j 1 gin , j 

Devices
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

C gin , j  C gin , j 1C gin , j 1

- each stage has the same effective fanout (Cout/Cin)

- each stage has the same delay

Devices
Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
f N
 F  C L / C gin,1

Effective fanout of each stage:

f NF
Minimum path delay


t p  Nt p 0 1  N F /  
Devices
Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f 38 2

Devices
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
C L  F  Cin  f Cin with N 
N

ln f
t p 0 ln F  f  
 1/ N

t p  Nt p 0 F /   1   
  ln f ln f


t p t p 0 ln F ln f  1   f
  0
f  ln f 2

For  = 0, f = e, N = lnF f  exp1   f 

Devices
Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp1   f 
fopt = 3.6
for =1

Devices
Impact of Self-Loading on tp
No Self-Loading, =0 With Self-Loading =1

60.0

40.0
u/ln(u)

x=10,000

x=1000

20.0 x=100

x=10

0.0
1.0 3.0 5.0 7.0
u

Devices
Normalized delay function of F


t p  Nt p 0 1  N F /  

Devices
 Buffer Design
N f tp
1 64 1 64 65

1 8 64 2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

Devices
Nothing comes for free:
 What about power consumption and
area?
 Delay vs. Area and Power

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Thanks……….

Devices