FPGA Based System Design: PVL109

Dr. Bharat Garg

Assistant Professor, ECED
 Lecture-4

• VHDL Data Types

• VHDL Objects
 VHDL Data Types

• All declaration of VHDL ports, signals, and variables must

specify their corresponding type or subtype

• Example: signal A,B: std_logic;

 VHDL Data Types

Types

Composite
Access
Scalar
Array Record

Integer Real Enumerated Physical

 VHDL Data Types: Integer data type

• Variables and signals of type integer can only be assigned integers

within a simulator-specific range.

• In the above example, the first two variable assignments are valid
since they assign integers to variables of type integer.

• The last variable assignment is illegal because it attempts to assign a

real number value to a variable of type integer.
 VHDL Data Types: Real data type

• Minimum range for any implementation as defined by standard:

-1.0E38 to 1.0E38

• Example assignment to a variable of type real:

 VHDL Data Types: Enumerated data type

• The basic enumerated data types accepted by Xilinx Synthesis

Tool (XST) are:
– BIT ('0','1')
– BOOLEAN (false, true)
– STD_LOGIC ('U','X','0','1','Z','W','L','H','-')

‘0’ : logic 0
‘1’ : logic 1
‘-’ : Don’t care
'U': uninitialized,
'X': unknown
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
‘H': Weak signal that should probably go to 1
 VHDL Data Types: Enumerated data type

• User specific list of possible values

• Example declaration and usage of enumerated data type:

• The enumerated data type allows a user to specify the list of legal
values that a variable or signal of the defined type may be assigned.
 VHDL Data Types: Physical data type
• Example of physical type declaration:

• The physical data type is used for values which have associated units.
• The designer first declares the name and range of the data type and then
specifies the units of the type.

• Notice there is no semicolon separating the end of the TYPE statement and the
UNITS statement.

• The line after the UNITS line states the base unit of the type. The units after the
base unit statement may be in terms of the base unit or another already
defined unit.

• The only predefined physical type in VHDL is time.

 VHDL Data Types: Array

• Used to group elements of same type into a single VHDL object.

• Range may be unconstrained in declaration
– Range would then be constrained when array is used
• Example declaration of one dimensional array (vector)
 Cont’d...

• The array is declared in a TYPE statement. There are

numerous items in an array declaration
– The first item is the name of the array.
– Second, the range of the array is declared.
• The keywords TO and DOWNTO designate ascending or descending indices,
respectively, within the specified range.
– The third item in the array declaration is the specification of the data
type for each element of the array.

• Example one-dimensional array using DOWNTO

 VHDL Data Types: Record
• Used to group elements of possibly different types into a single VHDL
object
• Elements are indexed via field names
• Example of record declaration and usage:
 VHDL Data Types: Access

• In brief, the access type is similar to a pointer in other programming

languages in that it dynamically allocates and deallocates storage space
to the object.

• This capability is useful for implementing abstract data structures

(such as queues and first-in-first-out buffers) where the size of the
structure may not be known at compile time.

• The VHDL access type will not be discussed in detail in this module.
 VHDL Data Types: Subtype

• VHDL subtype allows for user defined constraints on a data type.

– e.g. a subtype based on an unconstrained VHDL type

• May include entire range of base type

• Assignments that are out of the subtype range are illegal

– Range violation detected at run time rather than compile time because only base
type is checked at compile time

• The syntax and an example of a subtype declaration are shown above.

 VHDL Objects

• There are four types of objects in VHDL

– Constants
– Variables
– Signals
– Files
• The scope of an objects is as follows
– Objects declared in a package are available to all VHDL description
that use the package
– Objects declared in an entity are available to all architecture
associated with that entity.
– Objects declared in architecture are available to all statements in
that architecture
– Object declared in a process are available only within that process
VHDL Objects: Constant
 VHDL Objects: Variable

• Provide convenient mechanism for local storage

– E.g. loop counter, intermediate values

• Scope is process in which they are declared

• All variable assignment take place immediately

– No delta or user defined delay is incurred
• Declaration Syntax:

• Declaration example:
 VHDL Objects: Signal
• Used for communication between components

• All VHDL signal assignments require either delta delay

or user defined delay before new value is assumed.

• Declaration Syntax:

• Declaration example:
 VHDL Objects: Variable vs. Signal
• A key difference between variables and signal is the
assignment delay
 VHDL Objects: Variable vs. Signal
• In this example, variables are used to achieve the same functionality as
the example in the previous slide

• However, that in this example, the order in which the statements

appear within the process is important because the two statements
are executed sequentially, and the process will only be executed once as
a result of the single change in a.
 VHDL Objects: File

• Files provide the way for a VHDL design to communicate with host
environment

• File declaration make a file available for use to a design.

• File can be opened for reading and writing

• The package TEXTIO defines powerful routine handling I/O of test files