Memory Testing

AGENDA:

• Introduction
• Parametric Testing
• Functional RAM Chip Model
• Reduced Functional Model
• Scope of RAM Testing
• RAM Fault Models
Introduction
 Memories (RAM) are at the forefront of commercial electronic designs

 Memories are the most numerous IPs used in SOC designs

 Memory testing has to prove that the circuits under test behave as designed, it consists of:
Parametric tests which concern voltage/current levels and delays on the IO pins of the
chip
Functional testing including dynamic testing
Parametric Testing

 Contact test  Rise and fall

 Power  Zero defect
time approach
consumption  Setup and hold
 Leakage test  Use to detect
 Threshold test time some defects
 Output drive  Delay test not handle by
current test  Speed test functional
 Output short testing
current test

DC Parametric AC Parametric
IDDQ Testing
Testing Testing
Functional RAM Chip Model
Address Refresh

Address latch Column decoder Refresh logic

Row Memory Write driver

decoder Cell Array

Sense amplifiers Data register

R/W
and
Data out Data in CE
Reduced Functional Model
Address

Address decoder

Memory cell array

Read/write logic

Data
 Scope of RAM Testing
 Parametric Test: DC & AC

 Reliability Screening
 Long-cycle testing
 Burn-in: static & dynamic BI
 Functional Test
 Device characterization
 Failure analysis
 Fault modeling
 Simple but effective (accurate & realistic?)
 Test algorithm generation
 Small number of test patterns (data backgrounds)
 High fault coverage
 Short test time
 RAM Fault Models
 Address-Decoder Fault (AF)
 No cell accessed by certain address
 Multiple cells accessed by certain address
 Certain cell not accessed by any address
 Certain cell accessed by multiple addresses

 Stuck-At Fault (SAF)

The logic value of (a line or) a cell is always 0 (SA0) or 1 (SA1)
To detect memory cell's SAFs:
SA0: Write 1 Read 1 (w1 r1)
SA1: Write 0 Read 0 (w0 r0)
 Transition Fault (TF)
A cell fails to undergo a 0  1 transition (TFrise) or a 1  0
transition (TFfall) when it is written
To detect transition fault:
TFrise : w0 w1 r1
TFfall : w1 w0 r0
 RAM Fault Models
 Read Disturb Faults (RDF)
 A Cell is said to have a RDF if the read operation performed on the cell returns an
incorrect value while changing the contents of the cell to the wrong value.

 Deceptive Read Disturb Faults (DRDF)

 A Cell is said to have a DRDF if the read operation performed on the cell returns
the expected value while changing the contents of the cell to the wrong value

 Incorrect Read Faults (IRF)

 A Cell is said to have a IRF if a read operation performed on the cell returns the
incorrect value while keeping the correct stored value in the cell
 RAM Fault Models
 Recovery Fault (RF)
 Sense Amplifier Recovery Fault (SARF)
Sense amp saturation after reading/writing long run of 0 or 1

 Write Recovery Fault (WRF)

Write followed by reading/writing at different location resulting in
reading/writing at same location
Write-after-write recovery fault
Read-after-write recovery fault
 Disturb Fault (DF)
Victim cell forced to 0 or 1 if we read or write aggressor cell (may be the same
cell)