ELECTROMIGRATION

 It is the gradual displacement of metal atoms in a semiconductor.

 It occurs when the current density is high enough to cause the drift
of metal ions in the direction of the electron flow
 Failure mechanism – it decreases the reliability of chips
 Interconnects are getting thinner, running longer and switching at
gigahertz speeds - all of which amplify the effects of EM
 Miniaturization – thin interconnects – subject to high current density
 when an electric field is applied across a conductor, atoms
experience a force which is called the direct force (Fd irect).
 This force is a function of applied electric field
 Another force acting on atoms which is due to scattering of
electrons
 This force known as the electron wind
 This force is mainly a function of current density
 Ftotal = Fdirect + Fwind
How it happens ?
 Due to high current density, the electrons in the metal moves with
high acceleration
 These electrons transfer their momentum to other atoms and the
atoms get displaced from their original position and might create
voids and hillocks.
 Hillocks will create shorts
 voids will create opens between metal layers.

a) Void(open) b) hillock(short)
 It is a current related constraint

metal

 Each M having some current carrying capacity

 If current goes beyond that value leads to 3 problems:

o permanent damage of metal

o Opens
o shorts
FAILURE MECHANISMS

 NON UNIFORMITY IN LATTICE STRUCTURE OF INTERCONNECTS

 THERMAL ACCELERATING EFFECTS
 SELF HEATING EFFECT
NON UNIFORMITY IN LATTICE STRUCTURE
OF INTERCONNECTS
 There exists a non-uniformity of metal interconnect structures during
fabrication which may results in either void or hillocks.
 This non-uniformity is more dominant at vias /contacts
 A sudden change in conductor area through which current is
flowing ultimately affects the current density (J= I/A)
 If the current density is too high, it results a void that cause breaking
of line or hillocks that causes short-circuits to adjacent lines.
THERMAL EFFECT
 Once the void is formed on a line, the current density increases as
the area of conductor tends to reduce.
 This hampers the uniform temperature along the interconnect
 increases the local temperature which further accelerates the void
growth ultimately breaking the line
 The increase in temperature due to current density is termed as
Joule Heating which is directly proportional to the square of the
current density.
SELF HEATING EFFECT
 The heat generated by current carrying element
CAUSES

 HIGH FANOUT
 DRIVER SIZE
 FAST TRANSITION
 LONG NET
HIGH FANOUT

 Multiple fanouts switching at same time causes the driver cell to

demand for more current
 Leading to heat generation and displacement of more atoms
DRIVER SIZE

 X16 and X20 cells –supplies large currents

 Leading to heat generation
 Displacement of metal atoms and causes opens and shorts
FAST TRANSITION

 High velocity e which when collides with the atoms of interconnect

 causes them to break from the lattice structure leading to voids and
hillocks
 Clock nets have the highest probability of suffering from this issue as
it has high frequency signal passing through it with very high fanout
 LONG NET

 As the length of the interconnect increases, it’s resistance increases

(R=ρl/A).
 This high resistance causes a high localized temperature along the
net
 which further increases the resistance resulting metal reliability
problems and increase in Delta Temp value.
FIXES
Non-Default Rule (NDR) on the victim nets:
 Applying NDR will increase the metal width which will in-turn
increase it’s current carrying capability.

Routing on Higher Layers:

 Higher routing layers are less resistive
 More width and have higher current carrying capabilities making
nets less prone to electromigration
Use multi-cut Via or NDR via:
 Usage of multi-cut via will increase the via area
 reduces the resistance and also increases the reliability of the wire

Insert Buffer:
 Inserting a buffer or a pair-of-inverters will break the long nets and
reduces the resistance.
 We have to make sure that the EM affected path has enough
timing margin so that adding a buffer won’t degrade the timing
Driver Downsizing:
 DownsizIng the driver cell will reduce the current density in the
interconnects and reduces the risk of EM failure
 Though we have to make sure that downsizing the driver is not
affecting the timing or transition time in that path

Breaking fanout:
 splitting the fanout using buffers
 Generally, the buffer we add should be of same size or one size
lower than the driver so that timing is not much affected. Though
this is not a strict rule.
RedHawk 11.1.2
 Electromigration (EM) is the movement of material that results from the transfer of
momentum between electrons and metal atoms under an applied electric field.
 This momentum transfer causes the metal atoms to be displaced from their original
positions.
 This effect increases with increasing current density in a wire, and at higher
temperatures the momentum transfer becomes more severe.
 Thus in sub-100nm designs, with higher device currents, narrower wires, and
increasing on-die temperatures, the reliability of interconnects and their possible
degradation from EM is a serious concern

 The transfer of metal ions over time from EM can lead to either narrowing or
hillocks (bumps) in the wires.
 Narrowing of the wire can result in degradation of performance, or in
extreme cases can result in the complete opening of the conduction path.
 Widening and bumps in the wire can result in shorts to neighboring wires,
especially if they are routed at the minimum pitch in the newer
technologies.
 Foundries typically specify the maximum amount of current that can flow
through a wire under varying conditions. These EM limits depend on several
design parameters, such as wire topology, width, and metal density.
 EM degradation and EM limits depend on the temperature at which
interconnects operate, as well as on the material properties of the wires
and vias, on the direction of current flow in the wire, and on the distance of
the wire segment from the driver(s).
 One common EM check employed is to measure the average or DC current density
flowing through a wire and compare it against foundry-specified limits.
 Another common check employed is to measure the peak and RMS current flowing
through interconnects and check them against foundry-specified targets
 RedHawk provides a single platform approach in which to analyze EM of both power
grid and signal interconnects in a design.
 Power EM analysis is performed as an integral part of static and/or dynamic analysis
 Signal EM analysis, which is performed in a separate run, checks for average (uni-
directional or bi-directional), RMS, and peak current densities in all signal wires and vias
in a design.
RedHawk Methodology for Static Power
EM Analysis
 RedHawk™ automatically performs power EM analysis based on currents
obtained as part of static or dynamic voltage drop analysis. The primary
difference is that static EM analysis is based on true average current values
 RedHawk checks the actual current density for METAL wires, or current per
cut or area for a VIA segments, against the EM limit specified in the
technology file.
Setting Up EM Limits

 For a metal layer, the current density limit is

 defined as the current flowing per unit width. It can be specified in the tech file, as in the
 following example:
 metal METAL1
 {
 Thickness 1.45
 Resistance 0.2343
 EM 2.7
 above PASS4
 }
 In the above example the current density limit for layer METAL1 is defined as 2.7.
Analyzing Static EM Analysis Results
 Once the simulation is performed you can click on the EM button in the
View Results panel to see the EM violations map
By default, RedHawk dumps only the top 1000 violations
 If you want to dump EM violations in a specific range, you can use the GSR
keyword EM_DUMP_PERCENTAGE. For example, if you specify
“EM_DUMP_PERCENTAGE 50 60" in the GSR, it dumps all violations having an EM
ratio between 50% and 60% in the file adsRpt/Static/<design_name>.em.
 In the EM report file RedHawk reports all METAL EM violations using the following
format.
 #Layer #End-to-end_coordinates #EM_Ratio #Net #Width
 METAL4 (4905.670,3398.849 4905.670,3400.562) 469.016% VDD 25.000
 This report is also available using the GUI menu command Results -> List of Worst
EM.
Methodology for Dynamic Power EM
Analysis
 In dynamic analysis, RedHawk can perform EM wire/via analysis based on
three different types of currents: peak, RMS or average.
 The GSR keyword EM_MODE is used to select the mode for the current
analysis. By default, RedHawk automatically performs
 an EM analysis on the specified EM_MODE (Avg, RMS or Peak).
 Analyzing Dynamic Power EM
Violations
 Dynamic EM analysis generates reports of the worst EM violations for each mode with the same filenames
(<design>.em.worst.peak, *.avg, and *.rms) as in static analysis,located in the adsRpt/Dynamic directory.
 An example report generated after performing EM analysis for PEAK mode is shown below:
 EM MODE is PEAK
 # This file reports the EM violations, i.e. EM_Ratio =
 Actual_Current_Density/Current_Density_Limit > 100% (default or from
 “em_report_percentage”) for wire pieces and vias in decreasing order. Unit
 used for coordinates and dimensions is um.
 # For wires: #layer #end-to-end_coordinates #EM_Ratio #net #width
 # Blech_length
 # For vias: #via_name #x-y_coordinates #EM_Ratio #net #blech_length
 METAL3 (886.190,1018.712 887.192,1018.712) 1081.01% VDD 2.003 141.951
 METAL3 (885.190,1020.695 886.190,1020.695) 1081.01% VDD 2.000 141.951
 METAL3 (2944.210,2479.555 2944.210,2480.055) 1024.24% VDD 2.000 10.500
 METAL3 (2942.980,2479.305 2942.980,2479.555) 1024.24% VDD 0.500 10.500
 METAL3 (1108.770,2479.555 1108.770,2480.055) 1023.81% VDD 2.000 10.500
 METAL3 (1107.540,2479.305 1107.540,2479.555) 1023.81% VDD 0.500 10.500
 RedHawk calculates the actual current density as follows:
 Actual I density = (Current/Eff_Width) = 219.664 /(25-0.016) = 8.7922 mA/u
 And the EM limit for METAL4 in the tech file is defined as 1.874 mA/u.
 RedHawk calculates the EM_Ratio using the following equation.
 EM_Ratio = 100 * (Actual density of current) / (EM limit in tech file).
 Therefore
 EM_Ratio = 100 * 8.7922 / 1.874 = 469.2
 For VIAs, RedHawk reports the EM violations in the following format:
 #Via_name #x-y_coordinates #EM_Ratio #net
 via via3Array_87 (3154.820,893.390) 172.29% GND
 The EM_ratio of a VIA layer is calculated as follows (percentage):
 EM_Ratio = (Current through the VIA)*100 /(EM limit)
 Fixing Power EM Violations
 EM violations are mostly caused by weak power grid connections feeding current to high power-
consuming regions or blocks in the design
 If this is the case, increasing the metal width to reduce the current density is a typical solution.
 You also can provide additional straps for the current supply, thereby reducing the current-per-
strap value
 Layer switching is another option; typically, upper metal layers in the technology have
higher current driving capability (due to greater thickness). So you can use these layers
for designing the major power grids (grids with higher current flow) in the design

 for a via EM violation,

 you can increase the number of vias to fix potential EM issues
 An example EM violation is caused by an
 insufficient number of vias between the power straps. More vias are added in this
area using the 'Add Via' option in RedHawk to fix the problem,
signal EM analysis
 Redhawk
 RedHawk Input Files
 1. Technology file (*.tech)
 2. Global Switching Configuration file (*.gsc)
 3. Global System Requirements file (*.gsr)
 4. Pad instance, cell, or location files (*.pad, *.pcell, *.ploc)
 5. Library technology files
 6. Design netlist files
 7. Synopsys library files
Technology file (*.tech)
Global Switching Configuration file (*.gsc)

 The Global Switching Configuration file specifies the switching status of

blocks, instances,
 and voltage domains in the design for both power calculation and
simulation steps, using
 the fixed state keywords or multi-state definitions from SIM2IPROF, AVM, or
APLMMX.
Global System Requirements file (*.gsr)

 The Global System Requirements (GSR) file contains the input design file
specifications,
 operating conditions for chip for power calculation, static IR drop and EM
analysis, and
 dynamic voltage drop analysis.
Pad instance, cell, or location files (*.pad,
*.pcell, *.ploc)

 A single input file now can be used to specify all pad, power/ground and
I/O input data

 For original .ploc format with P/G_net name specified

 # <pin_name> <x_loc> <y_loc> <layer> <PG_net name>
 Vdd1 60.9 1214.67 M4 VDD1
 Vdd2 69.6 1214.67 M4 VDD2
 Vss 80 1214.67 M2 VSS
Library technology files

 The Library Exchange Format, or .lef file, defines the IC process technology
a
 following is an example of a set of LEF files:
 LEF/blocks.lef
 LEF/tsmc13hd.lef
 LEF/tsmc13hd_10_2a.lef
Synopsys library files

 The Synopsys Libraries files define the directory path for the set of Synopsys
Library files (.lib), which are used for cell definition and power calculation.
 pin <pin_name>
{
capacitance <pF>
direction [ input | output | inout ]
function “<function_type>”
type [ clock | scan ]
vector “<inputPinName> <clockPinName> : <pinName> [0 | 1] ...”
}
}
GUI Log Message Viewer
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