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6 227 2005
6 227 2005
6 227 2005
Feed-back
filter (FBF)
State trellis
Allowed transition
diagram
between states
State
Sample time
instants
Linear equalization, zero-forcing algorithm
Basic idea: Z f B f H f E f
B f
H f
E f
Z f
0 fs = 1/T f
Zero-forcing equalizer
Transmitted r k z k
impulse Communication Equalizer
sequence channel Input to
decision
FIR filter contains FIR filter contains
Overall circuit
2N+1 coefficients 2M+1 coefficients
channel
M
Coefficients of
equivalent FIR filter
fk
m M
cm hk m ( M k M )
J E ek
2
The aim is to minimize:
Input to Estimate
decision of k:th
circuit symbol Error
ek
+
zk bˆk
Channel Equalizer
s k r k z k b̂ k
MSE vs. equalizer coefficients
J E ek
2
quadratic multi-dimensional function of
equalizer coefficient values
J
Illustration of case for two real-valued
c2 equalizer coefficients (or one complex-
valued coefficient)
c1
Rc opt p
R E r k r*T k
r k rk , rk 1 ,..., rk M 1
T
where
p E r k bˆk
*
M samples
ek
c M c1 M cM 1 cM
+
zk bˆk
zk
r k Equalizer filter
e j bˆk
Coefficient Phase
updating synchronization +
ek
Godard
Proakis, Ed.3, Section 11-5-2
Minimize:
M
J E ek ek zk bk cm rk m exp j bˆk
ˆ
2
m M
Least-mean-square (LMS) algorithm
(derived from “method of steepest descent”)
for convergence towards minimum mean square error (MMSE)
ek
2
ek
2
ek
2
ek ek ek
2
Phase: i 1 i
2 2M 1 1
equations Iteration index Step size of iteration
LMS algorithm (cont.)
j M
Re cn i 1 Re cn i 2 Re e cm rk m bˆk rk n e j
m M
j M j
Im cn i 1 Im cn i 2 Im e cm rk m bk rk n e
ˆ
m M
ˆ j M ek
i 1 i 2 Im bk e cm rk m
m M
Effect of iteration step size
smaller larger
M Q
where ek zk bˆk c
m M
r
m k m qn bˆk n bˆk
n 1
LMS
hˆm cm
c0 c1 cM 1 cM
algorithm
rk rˆk
+
1. Acquisition phase
Uses “training sequence”
Symbols are known at receiver, bˆk bk .
2. Tracking phase
Uses estimated symbols (decision directed mode)
Symbol estimates are obtained from the decision
circuit (note the delay in the feedback loop!)
Since the estimation circuit is adaptive, time-varying
channel coefficients can be tracked to some extent.
Training
symbols Estimated channel coefficients
(no
errors)
ĥ m b̂ k
Channel Equalizer
estimation & decision
circuit circuit
r k
Received signal samples “Clean” output symbols
Theoretical ISI cancellation receiver
(extension of DFE, for simulation of matched filter bound)
rk P Filter matched to
bˆk
sampled channel +
impulse response
r t Matched NW
y k MLSE
b̂ k
filter filter (VA)
fˆ k
Channel
estimation circuit
f k
2
K 1
N
1 1 N
p y b, f p yk b, f
ˆ ˆ ˆ ˆ exp 2 yk f n bk n
ˆ ˆ
2 2
N 2 N
k 1 k 1 n 0
Objective: This is allowed since
Metric to be
find symbol noise samples are
minimized
sequence that uncorrelated due to NW
(select best b̂
..
maximizes this (= noise whitening) filter
using VA)
probability
MLSE-VA receiver structure (cont.)
At time k-2 1 0 0 1 0 0
At time k-1 1 0 0 1 0 0 1
At time k 1 0 0 1 0 0 1 1
:
16 states
Bit detected at time instant
Number
The ”best” state
of states
sequence is
m K 1 estimated by
means of Viterbi
Alphabet algorithm (VA)
size
k-3 k-2 k-1 k k+1