LOW POWER CMOS

CIRCUIT DESIGN

BY
C.RADHIKA
09VL03F
 CONTENTS

Introduction
Factors of power dissipation in cmos
Techniques to reduce power dissipation
Advantages
Disadvantages
Conclusion
 INTRODUCTION

Need for low power VLSI design

 Scale of integration
 Density
 Operating frequency
 Demand for portable electronic
devices
 FACTORS OF POWER
DISSIPATION

Charging and discharging capacitance

Short circuit current
Leakage current
Static current
 CHARGING AND DISCHARGING OF
CAPACITANCE

• Power dissipated per clock cycle=cl*v²

• Power dissipated by multiple
capacitors=ctotal*v²*f
 SHORT CIRCUIT CURRENT IN CMOS

SHORT CIRCUIT CURRENT OF AN

INVERTER:
SHORT CIRCUIT CURRENT VARIATION WITH
OUTPUT LOAD
Large output capacitance
Less short circuit current and high total
current
SHORT CIRCUIT CURRENT VARIATION WITH
INPUT SLOPE
As slope increases current envelop width and
peak increases
High input slope better performance
CMOS LEAKAGE CURRENT
REVERSE BIASED PN JUNCTION
CURRENT:
Parasitic effect of bulk of cmos
Current equation: Ir= Is(exp(v/v )-1)
th

Order of pA/µm²
Dynamic current per an inverter : in order of µA
Depends on temperature , junction area
SUBTHRESHOLD CHANNEL LEAKAGE CURRENT:
VGS<Vth
Very small compared to capacitor charging and
discharging currents
Limiting factor in low voltage and low power
chip design
Isub=I0*exp((vgs-vth)/(αvth))
Depends on Vgs,Vds,temperature
STATIC CURRENT
Peudo NMOS logic
Efficient area usage
Trade off between power and area
TECHNIQUES TO REDUCE POWER
DISSIPATION
Reduce switching voltage
 P=CV²f
 Noise immunity
Reduce capacitance(possible at material ,
physical design , circuit techniques)
Reduce switching frequency
 Alternate logic implementation
 Coding methods , counting sequence ,
data representation
TRANSISTOR SIZING
For dynamic power reduction
 Same as area reduction
 Small size gates
 Gain
For leakage power reduction
 Varies with Vth , channel length
 Depends on logic state
 Trade off for speed