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BJT and FET Review
BJT and FET Review
BJT and FET Review
Magday Jr
Bipolar Junction Transistor
(BJT)
1
Course Outline
2
HISTORY OF TRANSISTOR
• In 1904, the vacuum-tube diode was introduced by J. A.
Fleming.
• In 1906, Lee De Forest added a third element, called the
control grid, to the vacuum diode, resulting in the first
amplifier, the triode.
• Production rose from about 1 million tubes in 1922 to about
100 million in 1937.
• In the early 1930s the four-element tetrode and five-element
pentode gained prominence in the electron-tube industry.
• In the years to follow, the industry became one of primary
importance and rapid advances were made in design,
manufacturing techniques, high-power and high-frequency
applications, and miniaturization.
BIPOLAR JUNCTION TRANSISTOR
(BJT)
• A semiconductive device used for amplification and switching
applications.
• Dr. Bardeen
Born: Madison,Wisconsin,1908
PhD Princeton, 1936
6
BIPOLAR JUNCTION TRANSISTOR
(BJT)
• The term Bipolar is because two type of charges (electrons
and holes) are involved in the flow of electricity
n Base-Collector p
junction
p B (base) n
B (base)
Base-Emitter
n junction p
9
E (emitter) E (emitter)
Schematic Symbols
B B
E E
10
Transistor Operation
IB n IB
+ p + IB + IC = IE
n
IE
IE - 12
-
Problem1: A bipolar NPN transistor has a DC current
gain, (Beta) value of 200. Calculate the base
current Ib required to switch a resistive load of 4mA.
13
Transistor Operation
IB p IB
n IE = IB + IC
p
IE
IE 15
Transistor Characteristics and Parameters
+ DC = IC / IE
RB +
- VC
+ + -
VBB IB IE
C
-
--
16
Transistor DC Bias Circuit
Regions of BJT
1. Base
• Region to which carriers f
• low from emitter to collector
1017 dopants/cm3
• Moderately doped
2. Emitter
• Region from which carriers flow
• 1019 dopants/cm3
• Heavily doped
3. Collector
• Region to which carriers flow
• 1015 dopants/cm3
• Lightly doped
• Largest
Transistor Characteristics and Parameters
RB + +
- VC
+ + -
VBB IB IE
C
-
-
-
RB + +
- VC
+ + -
VBB IB IE
C
-
-
-
• VCE : dc voltage at
collector with 20
respect to emitter
BJT CURRENTS AND VOLTAGES
COMMON CONFIGURATIONS
b. Saturation Region
• both junctions are
forward biased
• switch on operation
for the transistor
BJT REGIONS OF OPERATION
c. Cut off Region
• both junctions are
reverse biased
• switch off operation for
the transistor
+
+
RB = 10k - VCC
+ + - 10V
VBB
-
5V -
+
RB VCB +
- VCE VCC
+ + -
IB
VBB IE
VBE -
-
+
+
RB = 10k - VCC
+ + DC = 50 - 10V
VBB
-
3V -
+
+
RB = 6.8k - VCC
+ + DC = 125 - 12V
VBB
-
1.5V -
DESIGN OPERATIONS
Rex Jason H. Agustin
55
BIASING PNP TRANSISTORS
Maximum Transistor Ratings
RC VBB
0
RB Vc
VCC
Vin r’e
Vb
VCC
VBB
WATER
JFET Construction
Drain Drain
Channel
Gate Gate
Source Source
P - CHANNEL N - CHANNEL
Junction Field-Effect Transistor
Drain Drain
D D
Gate G Gate G
p n p n p n
S S
n-channel p-channel
JFET schematic symbols
Drain Drain
Gate Gate
Source Source
N - CHANNEL P - CHANNEL
Biasing JFET
P P
Greater VGG
Less VGG
JFET Characteristics and Parameters
• Pinch-off voltage
• Shorted-Gate Drain Current (IDSS)
• Gate-Source Cutoff Voltage (VGS(off))
• JFET Drain Characteristic and Transfer
Characteristic Curve
2
VGS
ID I DSS 1
VP
William Bradford Shockley (1910 -1989) –
co-inventor of the first transistor and
formulator of the field effect theory
employed in the development of the
transistor and FET.
• Gate Resistance and Capacitance
VGS VGG
2
VGS
I D I DSS 1
VP
VDS VDD I DR D
Base Bias
Base Bias: Biasing equations
VGS I DR S
2
V
I D I DSS 1 GS
V
GS (off )
VDS VDD I D ( R D R S )
JFET With Self-Biasing
+VDD • Large RG is required to
prevent shorting of
input signal to ground
RD and to prevent loading
VG = 0 on the driving stage.
• VGS = -IDRS
RG + • VD = VDD - IDRD
RS_ IS
• VDS = VD - VS
= VDD - ID(RD+RS)
Example Problem # 2
• Find VDS and VGS in figure shown. For
the particular JFET in this circuit, the
internal parameter values such as gm,
VGS(off), and IDSS are such that a drain
current (ID) of approximately 5 mA is
produced. Another JFET, even of the
same type, may not produce the same
results when connected in this circuit
due to the variations in parameter
value.
Setting Q-Point of JFET
• First, determine ID for a desired value of VGS either by using
transfer characteristic curve or Shockley’s equation.
• Then calculate RS = |VGS/ID|
• For midpoint bias (i.e. ID = 0.5 IDSS), make VGS=VGS(off)/3.4
• To set VD = 0.5 VDD , pick RD = VDD/(2ID)
Example Problem # 3
• Determine the value of RS required to self-bias a p-channel
JFET with IDSS=25 mA and VGS(off) = 15V. VGS is to be 5 V
Voltage-Divider Bias
Voltage-Divider Bias: Biasing
equations
R2
VG VDD
R1 R 2
VG VGS
ID
RS
VDS VDD I D ( R D R S )
Voltage-Divider Bias
To keep the gate-source junction +VDD
reverse-biased, VS > VG
VS = IDRS
R1 RD ID
R2
VG VDD VG
R1 R2
VS = VG - VGS VS
R2
RS IS
VS VG VGS
ID
RS RS
Example Problem # 4
• Determine the ID and VGS for the JFET with
voltage-divider bias in Figure shown, given that
for this particular JFET the parameter values are
such that VD = 7V
Graphical Analysis of
Voltage-Divider Biased JFET
ID
For ID = 0, VS = IDRS = 0, and
IDSS VGS = VG - VS = VG
For VGS = 0,
VG VGS VG
Q VG ID
RS RS
RS
Draw the dc load line by
joining the two points and
VGS 0 VG extend it to intersect the
VGS(off)
curve to get the Q-point.
Q-Point Stability
• The transfer characteristic of a JFET can differ
considerably from one device to another of the
same type.
• This can cause a great variation of the Q-point,
and consequently, ID and VGS.
• With voltage-divider bias, the dependency of ID
on the range of Q-points is reduced (i.e. more
stable) because the slope is less than for self-
bias, although VGS varies quite a bit for both
circuits.
Metal Oxide Semiconductor FET
• The MOSFET differs from the JFET in that it has no pn junction
structure.
• The gate of the MOSFET is insulated from the channel by a
silicon dioxide layer.
• The two basic types of MOSFETs are depletion (D) and
enhancement (E).
• Because of the insulated gate, these devices are sometimes
called IGFETs.
Depletion MOSFET
Drain • n-channel D-MOSFET is
D usually operated in the
SiO2 n depletion mode with VGS
Gate p G < 0 and in the
n enhancement mode
S with VGS > 0.
Channel Symbol
Source • p-channel D-MOSFET
Basic structure of uses the opposite
n-channel D-MOSFET voltage polarity
Depletion/Enhancement MOSFET
• Depletion Mode: negative gate voltage applied to n channel
depletes channel of electrons, thus increasing its resistivity. At
VGS(off), ID = 0, just like n-channel JFET.
• Enhancement mode: when VGS > 0, electrons are attracted
into channel, thus increasing (enhancing) the channel
conductivity.
Enhancement MOSFET
Drain
Induced RD
SiO2 D Channel
p p
VDD
Gate n G n
p VGG p
S
Symbol
Source
THE END 99