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ch3 - 102802 17032020 051549am
ch3 - 102802 17032020 051549am
Hardware/Software Introduction
1
Introduction
• General-Purpose Processor
– Processor designed for a variety of computation tasks
– Low unit cost, in part because manufacturer spreads NRE
over large numbers of units
• Motorola sold half a billion 68HC05 microcontrollers in 1996 alone
– Carefully designed since higher NRE is acceptable
• Can yield good performance, size and power
– Low NRE cost, short time-to-market/prototype, high
flexibility
• User just writes software; no processor design
– a.k.a. “microprocessor” – “micro” used when they were
implemented on one or a few chips rather than entire rooms
Embedded Systems Design: A Unified 2
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Basic Architecture
– Datapath is general
– Control unit doesn’t PC IR
store the algorithm –
the algorithm is
I/O
“programmed” into the
Memory
memory
memory location
I/O
Memory
...
10
11
...
Embedded Systems Design: A Unified 4
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Control Unit
• Control unit: configures the datapath
operations Processor
– Sequence of desired operations Control unit Datapath
(“instructions”) stored in memory –
“program” ALU
Controller Control
• Instruction cycle – broken into /Status
several sub-operations, each one
clock cycle, e.g.: Registers
– Fetch: Get next instruction into IR
– Decode: Determine what the
instruction means
– Fetch operands: Move data from PC IR R0 R1
memory to datapath register
– Execute: Move data through the
ALU I/O
– Store results: Write data from 100 load R0, M[500] Memory
...
register to memory 500 10
101 inc R1, R0
102 store M[501], R1
501
...
Embedded Systems Design: A Unified 5
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Control Unit Sub-Operations
• Fetch Processor
ALU
into IR Controller Control
/Status
– PC: program
counter, always Registers
points to next
instruction PC IR
100 R0 R1
load R0, M[500]
– IR: holds the
fetched instruction I/O
• Decode Processor
ALU
instruction means Controller Control
/Status
Registers
PC 100 IR R0 R1
load R0, M[500]
I/O
ALU
memory to datapath Controller Control
register /Status
Registers
10
PC 100 IR R0 R1
load R0, M[500]
I/O
• Execute Processor
ALU
the ALU Controller Control
/Status
– This particular
instruction does Registers
I/O
ALU
register to memory Controller Control
/Status
– This particular
instruction does Registers
I/O
PC=100 Processor
Registers
10
PC 100 IR R0 R1
load R0, M[500]
I/O
PC=100 Processor
PC=101
Registers
Fetch Decode Fetch Exec. Store
ops results
clk
10 11
PC 101 IR R0 R1
inc R1, R0
I/O
PC=100 Processor
PC=101
Registers
Fetch Decode Fetch Exec. Store
ops results
clk
10 11
PC 102 IR R0 R1
store M[501], R1
PC=102
Fetch Decode Fetch Exec. Store I/O
ops results ...
100 load R0, M[500] Memory
clk 500 10
101 inc R1, R0 501 11
102 store M[501], R1 ...
Embedded Systems Design: A Unified 13
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Architectural Considerations
ALU
buses, memory data Controller Control
interface /Status
bit, even 64
• PC size determines I/O
ALU
period Controller Control
/Status
– Must be longer than
longest register to Registers
register delay in
entire processor PC IR
– Memory access is
often the longest I/O
Memory
Wash 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Non-pipelined Pipelined
Dry 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Fetch-instr. 1 2 3 4 5 6 7 8
Decode 1 2 3 4 5 6 7 8
Execute 1 2 3 4 5 6 7 8
Instruction 1
Store res. 1 2 3 4 5 6 7 8
Time
pipelined instruction execution
Processor Processor
• Princeton
– Fewer memory
wires
• Harvard
Program Data memory Memory
– Simultaneous memory (program and data)
program and data
memory access
Harvard Princeton
Memory
...
• Instruction Set
– Defines the legal set of instructions for that processor
• Data transfer: memory/register, register/register, I/O, etc.
• Arithmetic/logical: move register through ALU and back
• Branches: determine next PC value when not just PC+1
Embedded Systems Design: A Unified 21
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
A Simple (Trivial) Instruction Set
Immediate Data
Register-direct
Register address Data
Register
Register address Memory address Data
indirect
Data
execution MOV
MOV
R0, 1324
R1, file_name
--
--
system call “open” id
address of file-name
the OS L2:
• Development processor
– The processor on which we write and debug our programs
• Usually a PC
• Target processor
– The processor that the program will run on in our embedded
system
• Often different from the development processor
• Compilers
C File C File Asm.
– Cross compiler
File
• Runs on one
Compiler Assemble
processor, but
r generates code for
Binary Binary
File
Binary
File
another
File
• Assemblers
Linker
Debugger
Library
• Linkers
Exec.
Profiler
File
• Debuggers
Verification Phase
•
Implementation Phase
Profilers
Embedded Systems Design: A Unified 31
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Running a Program
Sources: Intel, Motorola, MIPS, ARM, TI, and IBM Website/Datasheet; Embedded Systems Programming, Nov. 1998
=
0
0
0
0
p
o
down Mov2 M[dir] = RF[rn]
01
00
to Fetch
10
00
to Fetch
aren’t usually built this way
Mov4 RF[rn]= imm
• Much more optimized, much
11
00
to Fetch
00
01
to Fetch
01
01
to Fetch
op IR[15..12] dir IR[7..0]
rn IR[11..8] imm IR[7..0]
Jz PC=(RF[rn]=0) ?rel :PC
rm IR[7..4] rel IR[7..0]
10
01
to Fetch
control
– register file holds each of the signals
RFwa
variables Controller RFw
(Next-state and RFwe
• Functional units to carry out control
logic; state register)
From all
output RFr1a
RF (16)
p
o
register) control
signals RFr1e
Mov3 M[rn] = RF[rm] RFr1a=rn; RFr1e=1;
to Fetch Ms=10; Mwe=1; 16
0
1
0
0
RFr2a
PCld Irld
RF[rn]= imm RFwa=rn; RFwe=1; RFs=10; PC IR RFr1 RFr2
Mov4 RFr2e
to Fetch PCinc
1
1
0
0
PCclr ALUs
Add RF[rn] =RF[rn]+RF[rm] RFwa=rn; RFwe=1; RFs=00;
ALU
to Fetch RFr1a=rn; RFr1e=1;
0
0
1
0
ALUz
RFr2a=rm; RFr2e=1; ALUs=00 2 1 0
Sub RF[rn] = RF[rn]-RF[rm] RFwa=rn; RFwe=1; RFs=00;
to Fetch RFr1a=rn; RFr1e=1;
1
0
1
0
RFrle=1;
FSM operations that replace the FSMD
FSMD
operations after a datapath is created Memory
A D
You just built a simple microprocessor!