Design of a 4-bit Barrel

Shifter
Crossbar switch
Design of ALU subsystem

Adder Element
4-bit datapath for processor
 Ak Bk Previous Carry Sum New Carry
Ck-1 Sk Ck

Design of 4-bit adder 0

0
0

1
0

0
0

1
0

1 0 0 1 0

1 1 0 0 1

0 0 1 1 0

0 1 1 0 1

1 0 1 0 1

1 1 1 1 1

From TT,
For sum, If Ak=Bk, then Sk = Ck-1 else Sk=Ck-1’
For carry, If Ak=Bk, then Ck = Ak = Bk* else Ck=Ck-1
Bk* represents Carry, Ck = 1 when Ak=Bk =1
Ck = 0 when Ak=Bk = 0
Standard Adder element

Sk with inverter and

Sk and Ck with respect to equation clock synchronized
 nmos layout
Total Number of transistor:
Multiplexer : 16
Inverter for inputs: 6
Inverter for sum : 2
Total : 24

cmos layout
24+16 = 40
Multiplexer:

Stick diagram of single MUX Layout of single MUX

Inverter:

nmos inverter nmos inverter cmos inverter

Butting contact Buried contact
Implementing ALU functions with an adder:

Adder can be utilized to implement other functions like subtract, EX-

OR, EX-NOR, AND, OR as explained:

Addition: directly possible (A+B)

Subtract: (A+ 2’s complement of B)
EX-OR: Sk = Ak Ꚛ Bk Ꚛ Ck-1 when Ck-1 is ‘0’, then, Ak Ꚛ Bk Ꚛ 0 = Ak Ꚛ Bk
EX-NOR: Sk = Ak Ꚛ Bk Ꚛ Ck-1 when Ck-1 is ‘1’, then, Ak Ꚛ Bk Ꚛ 1 = Ak Ꙩ Bk
AND: Ck= AkBk+BkCk-1+AkCk-1 , when Ck-1 is ‘0’, then, Ck= AkBk
OR: Ck= AkBk+BkCk-1+AkCk-1 , when Ck-1 is ‘1’, then, Ck= Ak + Bk
4 bit ALU

4-bit Adder 4-bit ALU

• Transistor 20+10 = 30T
• With inverters for inputs: 30+4+6=40 T
 • Transistor 20+10 = 30T
• With inverters for inputs: 30+4+6=40 T

• Transistor for S’: 14T

• With inverters for output: 14+10+4=28T
Symmetrical adder cell arrangement
Manchester Carry-chain

Adder cell based on pass/generate concept Manchester Carry chain element

Cascaded Manchester carry-chain elements with buffering
Adder Enhancement Technique:

• Carry Select Adder

• Carry Skip Adder

• Carry Look Ahead Adder

Carry Select Adders

6-bit CSA
• N-bit Adder, computation time is, T=nK 1 where K1 is the delay through one adder.
• If adder is divided into blocks, with each block contains 2 adder cells, T= K 1 n/2 +K2, where K2 is
delay through the MUX
• Let n-bit adder be divided into M blocks and let each block contain ‘P’ adder cells in series (i.e
n=MP)
• Completion time is the sum of the propagation delay through the MUXes, T= PK 1 +(M-1) K2
• To obtain Tmin, Differentiate w.r.t ‘M’ and equate to ‘0’
• For minimum value for T, M = √(nK1/K2)
Carry Skip Adder

Working
 Delay Calculation:

Critical path = (All MUX triggers without skip + first and last MUX
triggers with skip) + (All adders are ON without skip + skip
paths are enclosed between first and last block with skip)
T = (MK2 + 2K2) + [PK1 +(P-2) K1]
T = 2(P-1)K1 + (M+2)K2
Carry Skip Adder

Computation Time:

• T= 2(P-1)K1 + (M+2)K2

• To obtain Tmin, Differentiate

w.r.t ‘M’ and equate to ‘0’

• M= √(2nK1/K2 )
Carry Look Ahead Adder

• jh
Comparison of adder
Adder Type Computation Time Area Occupied Speed increase
factor

Ripple Carry Adder 32K A 1

Carry Select Adder 10K 2A 3
Carry Skip Adder 15K 1.5A 2
Carry Look Ahead Adder 7.5K >>A 4

Note: Here it is assumed that K1=K2=K

K1 = delay through adder cell
K2 = delay through MUX cell