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PEPENTIUM
PEPENTIUM
PENTIUM PROCESSOR
● The Pentium is a widely-used personal computer
microprocessor from the Intel Corporation. First offered in
1993, the Pentium quickly replaced Intel’s 486
microprocessor as the microchip-of-choice in
manufacturing a personal computer. The original Pentium
model includes two processors on one chip that contains
3.1 million transistors.
● Clock frequency ranging from 60 to 66 MHz
FEATURES OF PENTIUM PROCESSOR
● S (sign) flag holds the arithmetic sign of the result after an arithmetic
or logic executes.
● IOPL used in protected mode operation to select the privilege level for
I/O devices
● NW not write through selects the mode of operation for the data cache. Iof
NW = 1, the data cache is inhibited from cache write through
● AM alignment mask enables alignment checking when set , it only occurs for
protected mode.
● WP write protect protects users level pages against supervisor level write
operations. When WP = 1, the supervisor can write to user level segment.
● RESET- (input)
○ Force the CPU to begin execution at a known state.
● INIT – initialization (input)
○ The Pentium processor initialization input pin forces the Pentium
processor to begin execution in a known state.
○ The processor state after INIT is the same as the state after
RESET except that the internal caches, write buffers, and floating
point registers retain the values they had prior to INIT.
ADDRESS BUS
● A31;A3- ADDRESS bus lines
○ OUTPUT except for cache snooping
○ These are input lines when AHOLD & EADS# are active for Inquire Cycle
(snooping)
ADDRESS BUS
● BE7#:BEO#: Byte Enable lines (Outputs)
● Bytes Enables to enable each of the 8 bytes in the 64-bit data
path.
○ Helps define the physical area of memory or I/O accessed.
○ In effect a decode of the address lines A2-A0 which the Pentium does not
generate.
○ Which lines go active depends on the address, and whether a byte, word,
double word or quad word is required.
ADDRESS MASK
○ Even parity must be driven back to the CPU during inquire cycles
on this pin in the same clock as EADS#.
○ during reads ,the CPU samples the data bus when BRDY# is asserted.
● DP7:DP0 – Data Parity (I/O)
○ Even Parity Check. One for each byte of the data bus
○ The following are some of the signals which are valid when ADS# = 0
○ From power-on the ADS# signal should be asserted periodically when bus cycles
are running
Bus Control
● BRDY# - Burst Ready (input)
○ The bus ready input indicates that the external system has presented data on the data pins in
response to a read or that the external system has accepted the Pentium processor data in
response to a write request.
○ This signal ends the current bus cycle and is used to extend bus cycles to allow slow device
extra time.
○ If LOW (non-burst cycles), this signal ends the current bus cycle and the next bus cycle can
begin
○ If HIGH the pentium is prevented from continuing processing and wait state are added
Bus Cycle Definition
● M/I0#- memoryor Input/Output (output)
○ Distinguishes between memory and I/O cycles
○ The memory/ input-output is one of the primary bus cycle definition pins
■ 1 = memory cycle
■ 0 = input/output cycle
■ 1=data
■ 0= code/ control.
■ 1=write
■ 0=read
○ The L1 cache must be enabled using the CD bit for CR0 for Cache# to be
asserted low
○ The cache# signal could also be described as the burst instruction signal,
because the cache# signal (qualified with KEN#) results in a burst mode
tranfer of 32 bytes of code or data.
Bus Cycle Definition
● NA# - Next Address (input)
○ The CPU will not allow a bus hold when Lock# is asserted
○ In response to the bus hold request, the pentium processor will float most
of its output and input/output pins and asserts HLDA after completing all
outstanding bus cycles
○ Pentium processor will maintain its bus in its state until HOLD is de-
asserted.
Bus Arbitration
● HLDA Bus Hold Acknowledge (output)
○ External indication that the pentium output are floated