ADVANCED COMPUTER

ARCHITECTURE
PRESENTED BY,
FARHAN MUKHTIAR

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 SIMD
• SIMD (Single Instruction Multiple Data)
• SIMD, is a class of Parallel computers in Flynn's taxonomy.
• It describes computers with multiple processing elements
that perform the same operation on multiple data points
simultaneously.
• Three variations of SIMD:
• vector architectures,
• multimedia SIMD instruction set extensions,
• graphics processing units (GPUs).

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 Vector Architecture
• Vector architectures are easier to
understand and to compile to than other
SIMD variations,
• But they were considered too expensive
for microprocessors until recently.
• Registers are controlled by compiler
• Register files act as compiler controlled buffers
• Used to hide memory latency
• Leverage memory bandwidth
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Basic structure of a vector architecture

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Components of vector architecture
• Vector registers
‐Each register holds a 64‐element, 64 bits/element vector
‐ Register file has 16 read ports and 8 write ports
• Vector functional units
• Fully pipelined
• Data and control hazards are detected
• Vector load‐store unit
‐ Fully pipelined
‐ Words move between registers
‐ One word per clock cycle after initial latency
• Scalar registers
• 32 general‐purpose registers
• 32 floating‐point registers

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 Vector Execution Time
• Execution time depends on three factors:
‐Length of operand vectors
‐ Structural hazards
‐ Data dependencies
• VMIPS functional units consume one element
per clock cycle
• Execution time is approximately the vector
length

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 Vector Processor Advantages
• Each instruction generates a lot of work
• Reduces instruction fetch bandwidth
• Highly regular memory access pattern
• Interleaving multiple banks memory
for higher bandwidth
• No need to explicitly code loops
• Fewer branches in the instruction sequence

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 SIMD Instruction Set Extensions for
Multimedia
• Media applications operate on data
types narrower than the native word size
‐Graphics systems use 8 bits per primary color
‐Audio samples use 8‐16 bits
‐ 256‐bit adder
‐ 16 simultaneous operations on 16 bits
‐ 32 simultaneous operations on 8 bits