MPMC Unit-3

UNIT – 1
PART-A
1. RISC Vs. CISC
2. Von-Neumann & Harvard Architecture
3. Memory mapped I/O and Isolated I/O
4. Little-Endian and Big-Endian
PART-B
5. Low Power RISC- MSP 430 : Introduction & Variants of MSP 430 family
6. MSP430F2013 - Block diagram & features
7. Memory map of MSP430
8. MSP430 –CPU architecture & registers
9. Addressing modes of MSP430
10. Instruction formats & Instruction Timings of MSP430
11. Instruction set of MSP430
12. Sample Embedded system on MSP430
www.maheshelectronics.wordpress.com
Features and architecture considerations
• RISC Vs CISC :
RISC (Reduced Instruction Set Computer)) CISC (Complex Instruction Set Computer)
Supports lesser number of instructions. Supports greater number of instructions.
Supports few addressing modes for memory access and data transfer Supports many addressing modes for memory access and data transfer
instructions. instructions.
Single, fixed length instructions Variable length instructions
Instructions take fixed amounts of time for execution Instructions take varying amounts of time for execution
Instruction pipelining works effectively and increases the execution Instruction pipelining concept is not effectively works as different sizes and
speed. different execution times of instructions.
Orthogonal instruction set (allows each instruction to operate on any Non-orthogonal set (all instructions are not allowed to operate on any
register and use any addressing mode.) register and use any addressing mode.
More silicon usage since more additional decoder logic is required to

Less silicon usage and decoding logic is not complex.
implement the complex instruction decoding.
Because of large amount of different and complex instructions, the design

Because of the simple instructions, the design of compiler is easy.
of compiler is complex.
A larger number of registers are available. Limited no. of general purpose registers
• HARVARD ARCHITECTURE Vs VON-NEUMANN ARCHITECTURE :
It has separate buses for instruction as It shares single common bus for instruction
well as data fetching. This means that, and data fetching. This means that only one
the data memory and program memory set of addresses covers both data memory
are separated. and program memory. The memory map
shows the addresses at which each type of
memory is located.
Low performance as compared to Harvard
Easier to pipeline, so high performance can be achieve. architecture
First fetches the instruction and then fetches the data. The two separate fetches
It allows simultaneous access to the program and data memories. For instance, the CPU slows down the controller’s operation.
can read an operand from the data memory at the same time as it reads the next
instruction from the program memory. Because several memory cycles are needed to extract a full instruction from
memory, this architecture is intrinsically less efficient.
Since data memory and program memory are stored physically in different locations, no Accidental corruption of program memory may occur if data memory and
chances exist for accidental corruption of program memory program memory are stored physically in the same chip.
A problem with the Harvard architecture is that constant data (often lookup tables) must
be stored in the program memory because it is nonvolatile. This means that constants
The system is simpler and there is no difference between access to constant and
cannot be read in the same way as volatile values from the data memory. Special “table
variable data.
read” instructions must therefore be provided or part of the program memory is mapped
into data memory

Separate decoding logic is required, because separate buses and control signals are used No additional logic is required because, Same bus and control signals are used for
for accessing data memory and program memory accessing for both data memory and program memory.

Comparatively high cost Low cost
MEMORY MAPPED I/O & I/O MAPPED I/O :
I/O devices are mapped into the

system memory map. i.e Common I/O devices are mapped into a
address space for memory and I/O separate address space. i.e., there is
ports (The I/O ports are viewed as separate address space for memory
memory locations and are addressed and I/O ports.
likewise)
Different control signals are used for memory and I/O
The control signals used for memory operation and I/O operation are operations.
same.
M/IO =1 for memory operation
M/IO = 1 for both Memory and I/O operations
M/IO =0 for I/O operation

Less no. of instructions are for I/O access. ( only IN and OUT
All instruction which can access memory can be used to access I/O instructions)
ports.
The data transfer takes place between Accumulator and I/O port
The data can be moved from any register to I/O port and vice-versa. only
The arithmetic, logic and bit manipulation instructions which are No instructions are available for direct manipulation of I/O data.
available for data in memory can also be used for I/O operations. First the processor reads data from I/O port and then
Hence the processor can directly manipulate data from I/O port. manipulates.
Large number of I/O devices can be interfaced Less no. of I/O devices can be interfaced
Full address space can’t be used for addressing Memory, because some Full address space can be used for addressing Memory, because
locations are allotted for I/O ports. I/O locations are separated from memory.
The entire address bus must be fully decoded for every device, which Less logic is needed to decode a discrete address and therefore
increases the cost less cost
LITTLE-ENDIAN & BIG-ENDIAN PROCESSORS
Endianness specifies the order which the data is stored in the memory
by processor operations in a multi byte system.
Little-endian means lower order data byte is Big-endian means the higher order data
stored in memory at the lowest address and byte is stored in memory at the lowest and
the higher order data byte at the highest the lower order data byte at the highest
address. address.
2000H 2000H
2001H 2001H
2002H 2002H
2003H 2003H
.
INTRODUCTION TO MSP430 MICROCONTROLLERS:
• MAIN CHARACTERISTICS OF MSP430 MICROCONTROLLER
• Flash (or) ROM-based low-power MCUs

• CPU clock : 8/16 MHz
• Operating voltage : 1.8–3.6 V
• Power specification overview, as low as:
• 0.1 μA RAM retention
• 0.7 μA real-time clock mode operation
• 160 - 250 µA/MIPS at active operation
• Fast wake-up from standby mode in less than 1 µs.
• Device parameters
– Flash/ ROM options: 1 KB – 60 KB
– RAM options: 128 B– 8 KB
– GPIO options: 14 - 80www.maheshelectronics.wordpress.com
pins
INTRODUCTION TO MSP430 MICROCONTROLLERS:
• Other integrated peripherals:

• 10/12/16-bit Analogue-to-Digital Converter (ADC);
• 12-bit dual Digital-to-Analogue Converter (DAC);
• Comparator-gated Timers;
• Watch Dog Timer
• SPI, I2C, UART
• Operational Amplifiers (OP Amps)
• 16×16 multiplier
• Comparator_A
• Temp. sensor
• LCD driver
• Supply Voltage Supervisor (SVS)
• Brown out Reset
• 16 bit RISC CPU:
• Instructions processing on either bits, bytes or words;
• Compact core design reduces power consumption and cost;
• Compiler efficient;
• 27 core instructions;
• 7 addressing modes;
• Extensive vectored-interrupt capability.
BLOCK DIAGRAM OF MSP430 F2013/ F2003 MICROCONTROLLER
MSP430 part numbering:
VARIANTS OF MSP 430 FAMILY – 1XX, 2XX, 3XX, 4XX, 5XX:
VARIANT OF FAMILY POWER SPECIFICATIONS DEVICE PARAMETERS OTHER INTEGRATED PERIPHERALS
MSP430x1xx 0.1 μA RAM retention Flash/ROM options: 1–60 KB 12-bit DAC, up to 2 16-bit timers, WDT, brown-out reset, SVS,
0.7 μA real-time clock mode RAM options: 128 B– 2 KB USART module (UART, SPI), DMA, 16×16 multiplier, Comparator_A,
200 μA / MIPS active GPIO options: 14/22/48 pins Temp. sensor
Features fast wake-up from standby mode in less than 6 µs. ADC options: Slope, 10 & 12-bit SAR

MSP430F2xx 0.1 μA RAM retention Flash/ROM options: 1 KB–60 KB operational amplifiers, 12-bit DAC, up to 2 16-bit timers, watchdog
0.3 μA standby mode (VLO) RAM options: 128 B – 8 KB timer, brown-out reset, SVS, USI module (I²C, SPI), USCI module,
0.7 μA real-time clock mode GPIO options: 10/16/24/32/48 pins DMA, 16×16 multiplier, Comparator_A+, Temperature sensor
220 μA / MIPS active ADC options: Slope, 10 & 12-bit SAR, 16 & 24-bit Sigma Delta
Feature ultra-fast wake-up from standby mode in less than 1 μs

MSP430x3xx 0.1 μA RAM retention ROM options: 2–32 KB LCD controller, multiplier
0.9 μA real-time clock mode RAM options: 512 B–1 KB
160 μA / MIPS active GPIO options: 14/40 pins
Features fast wake-up from standby mode in less than 6 µs. ADC options: Slope, 14-bit SAR

MSP430x4xx 0.1 μA RAM retention Flash/ROM options: 4 KB– 60 KB 12-bit DAC, Op Amps, RTC, up to two 16-bit timers, watchdog
0.7 μA real-time clock mode RAM options: 256 B – 8 KB timer, basic timer, brown-out reset, SVS, USART module (UART,
200 μA / MIPS active GPIO options: 14/32/48/56/68/72/80 pins SPI), USCI module, LCD Controller, DMA, 16×16 & 32x32 multiplier,
Features fast wake-up from standby mode in less than 6 µs. ADC options: Slope, 10 & 12-bit SAR, 16-bit Sigma Delta Comparator_A, Temp. sensor

MSP430x5xx 0.1 μA RAM retention Flash options: up to 512 KB High resolution PWM, 5 V I/O's, USB, backup battery switch, up to
2.5 μA real-time clock mode RAM options: up to 66 KB 4 16-bit timers, watchdog timer, Real-Time Clock, brown-out reset,
165 μA / MIPS active ADC options: 10 & 12-bit SAR SVS, USCI module, DMA, 32x32 multiplier, Comp B, temperature
Features fast wake-up from standby mode in less than 5 µs. GPIO options: 29/31/47/48/63/67/74/87 pins sensor

MSP430x6xx 0.1 μA RAM retention Flash options: up to 512 KB USB, LCD, DAC, Comparator_B, DMA, 32x32 multiplier, power
2.5 μA real-time clock mode RAM options: up to 66 KB management module (BOR, SVS, SVM, LDO), watchdog timer, RTC,
165 μA / MIPS active ADC options: 10 & 12-bit SAR Temp sensor
Features fast wake-up from standby mode in less than 5 µs. GPIO options: 74/90 pins

Memory map of MSP430
MSP430 –CPU architecture & registers
• The cpu features
– Calculated branching
– Table processing
– 27 RISC instructions
– 7 addressing modes
– All instructions use all the addressing modes
– Full register access
– Single cycle register operations (RISC)
– Direct memory-to-memory transfers
– Constant generator provides most used values
There are 16 registers

 Contents are 16-bits
 User has access to all
registers
 4 registers are special
purpose
Note bus structure
 MDB – Memory Data
Bus
 MAB – Memory Address
Bus
 Also have 2 internal
bussed to deliver 2
operand to ALU
Diagram is called the datapath
of the processor
• R4 thru R15
– Registers are indistinguishable
– Can be used as
• Data Registers
• Address Registers
• Index values
– Can be accessed with byte or word instructions
– There is Register-Byte operation and Byte-Register
operation – covered later
• R0: Program Counter (PC) :
• The 16-bit Program Counter (PC/R0) points to the
next instruction to be fetched from memory and
executed by the CPU.
• The Program counter is incremented by the number
of bytes used by the instruction (2, 4, or 6 bytes,
always even).
• R1: Stack Pointer (SP)
• The stack memory is a memory block where the
data is stored in LIFO manner.
• The Stack Pointer (SP/R1) holds the address of the
stack-top.
• In the MSP430, as in many other processors, the
stack is allocated at the top of the RAM and grows
down towards low addresses.
• Operation of the Stack :
The operation of the stack is illustrated in the
following figure. The specific addresses are for
MSO430F2013 with 128 Bytes of RAM are from
0x0200 to 0x027F. Hence, Before the execution, the
initially the value of SP = 0x0280
• R2: Status Register (SR)
• The Status Register (SR/R2) stores the status bits
and control bits.
• C : Carry Flag Z : Zero Flag

• N : Negative Flag V: Signed overflow flag
• Enable Interrupts :: Setting the general interrupt
enable (GIE) bit enables maskable interrupts.
• Clearing the bit disables all maskable interrupts.
• There are also nonmaskable interrupts, which
cannot be disabled with GIE.
• Control of Low-Power Modes :
• SCG1 (System clock generator 1) : When set, turns
off the SMCLK.
• SCG0 (System clock generator 0) : When set, turns
off the DCO dc generator, if DCO-CLK is not used for
MCLK or SMCLK.
• OSCOFF (Oscillator OFF ) : When set, turns off the
LF XT1 crystal oscillator,
• if LFXT1-CLK is not used for MCLK or SMCLK.
• CPUOFF : When set, turns off the CPU.
• R2/R3: Constant Generator Registers (CG1/CG2)
• Depending of the source-register addressing modes (As) value, six commonly used constants
can be generated without a code word or code memory access to retrieve them.
• The constants below are chosen based on the bit (As) of the instruction that selects the
addressing mode.
•
Register Addressing mode Constant
R2 10 +4
R2
11 +8
R3
00 0
R3
01 +1
R3
10 +2
R3
11 -1 (FFFF)
MSP430 –Addressing modes
• MSP430 addressing modes
– Addressing mode – the way in which the operand(s) of
an instruction are accessed, i.e., the effective addresses
are calculated.
– 7 modes supported
• Register Mode – (Rn) – operands are in registers
• Immediate Mode – #N – The operand is part of the
instruction
– Instructions have format OPCODE #OPERAND
• Absolute Mode – &ADDR – The address of the
operand is given by the word following the opcode
– Instructions have format OPCODE &ADDRESS
MSP430 –Addressing modes
• Remainder of addressing mode
– Indexed Mode – X(Rn) – (Rn+X) points to (is the address
of) the operand. The value X is the next word in the
instruction stream after the OPCODE.
– Symbolic Mode – ADDR – (PC+X) points to the operand.
X is the next word.
– Indirect Register Mode - @Rn – Rn is used as a pointer to
the operand.
– Indirect Autoincrement - @Rn+ - Rn is used as a pointer
to the operand. After access Rn is incremented by 1
for .B instructions and by 2 for .W instructions
INSTRUCTION FORMATS OF MSP430 :
• Each instruction has 2- parts:

• The task to be performed – called as Operation code
(Opcode)
• The data to be operated on – called as Operand.
• Instruction format:
OPCODE OPERAND
• There are three core-instruction formats:

»Dual-operand
»Single-operand
»Jump
INSTRUCTION SET OF MSP430
• The instructions can be classified as follows:

1. Movement Instructions (Data Transfer)
2. Arithmetic and Logic Instructions
3. Shift and Rotate Instructions
4. Control Transfer instructions
(Branch/Subroutine/Interrupt)
Movement Instructions (Data Transfer)
Instruction Operation Example
Copies data from source to destination mov.w R5, R6

1 mov.w src, dst
dst  src R6  R5
Push data onto stack push.w R5
2 push.w src ( first the SP is decremented by 2 and the source content is stored at stacktop) SP  SP-2
@ --SP = src @ SP  R5
Pop data from stack push.w R6

( first the content of stacktop is moved to destination and SP is incremented by
3 pop.w dst R6  @ SP
2)
dst = @SP + + SP  SP+2
Arithmetic and Logic Instructions
Binary Arithmetic Instructions with Two operands
Add the content of source to destination

1 add.w src, dst add.w R5, R6
dst  dst + src
Add with carry

2 addc.w src, dst addc.w R5, R6
dst  dst + (src + C)
Add carry bit to the destination

3 adc.w dst adc.w R6
dst  dst + C
Subtract the content of source from destination

4 sub.w src, dst sub.w R5, R6
dst  dst - src
Subtract with borrow

5 subc.w src, dst subc.w R5, R6
dst  dst –( src + C)
Subtract borrow bit from the destination

6 sbc.w dst sbc.w R6
dst  dst – C
Compares source and destination.
Performs ( dst – src), but Only flags are changed

7 cmp.w src,dst cmp.w R5,R6
If dst > src : C=0, Z=0
If dst < src : C=1, Z=0
If dst = src www.maheshelectronics.wordpress.com
: C=0, Z=1
Arithmetic Instructions with One operand
Clear destination clr.w R6

1 clr.w dst
dst  0 R6  0
The content of destination is decremented by 1 dec.w R6

2 dec.w dst
dst  dst – 1 R6  R6 - 1
Double decrement
decd.w R6
3 decd.w dst The content of destination is decremented by 2
R6  R6 – 2
dst  dst – 2
The content of destination is inccremented by 1 inc.w R6

4 inc.w dst
dst  dst + 1 R6  R6 + 1
Double increment
incd.w R6
5 incd.w dst The content of destination is inccremented by 2
R6  R6 + 2
dst  dst + 2
Test ( compare with zero)
Performs ( dst – 0), but Only flags are changed

6 tst.w dst tsd.w R6
If dst > 0 : C=0, Z=0
If dst < 0 : C=1, Z=0
If dst = 0 : C=0, Z=1
Decimal Arithmetic & logical Instructions
These instructions are used to perform BCD addition
Perfroms the decimal addtion of destination and source with carry dadd.w R5, R6
1 dadd.w src, dst
dst  dst + src + C R6  R6 + R5+C
Performs the decimal addition of destination and carry. dadc.w R6

2 dadc.w dst
dst  dst + C R6  R6 + C
Logic Instructions with ONE operand
Invert destination
1 inv.w dst Performs bit-wise NOT operation (1’s complement) inv.w R6
dst  ~dst
Logic Instructions with Two operands
Performs bit-wise logic AND operation

1 and.w src, dst and.w R5, R6
dst  dst AND src
Performs bit-wise logic Ex-OR operation

2 xor.w src, dst xor.w R5, R6
dst  dst XOR src
Performs bit-wise Test operation

3 bit.w src, dst bit.w R5, R6
It performs Logic AND operation, But Only flags are affected
Set bits in destination
The source operand and the destination operand are logically ORed. The result is placed
4 bis.w src, dst into the destination. The source operand is not affected. bis.w R5, R6
dst  dst OR src
Clear bits in destination
The inverted source operand and the destination operand are logically ANDed. The result
5 bic.w src, dst is placed into the destination. The source operand is not affected bic.w R5, R6
dst  dst AND ~src
Byte manipulation
Swap upper and lower bytes

1 swpb dst The high and the low byte of the operand are exchanged swpb R6
dst.15:8 ↔ dst.7:0
Extend sign of lower byte

The sign of the low byte of the operand is extended into the high byte
2 sxt dst dst. 15:8  dst.7 sxt R6
If dst.7 = 0: high byte = 00 H afterwards
If dst.7 = 1: high byte = FF H afterwards
Operations on Bits in Status Register
These instructions are used to set or clear the flags in Status Register. All these
instructions are emulated instructions.
Instruction Operation Flag affected
1 clrc Clear Carry bit C=0
2 clrn Clear Negative bit N=0
3 clrz Clear Zero bit Z=0
4 setc Set Carry bit C=1
5 setn Set Negative bit N=1
6 setz Set Zero bit Z=1
7 dint Disable General Interrupts GIE = 0
8 eint Enable Generalwww.maheshelectronics.wordpress.com

Interrupts GIE = 1
Shift and Rotate Instructions
Instruction Description Operation
rla dst Arithmetic shift Left
rra dst Arithmetic shift Right
rlc dst Rotate Left through Carry
rrc dst Rotate Right through Carry
Control Transfer Instructions
Instruction Description Operation

1 br src Branch ( go to) PC  src

SP  SP-2
2 call src Call Subroutine @ SP  PC
PC  src

PC  @ SP
3 ret Return from Subroutine
SP  SP+2

SR  @ SP
Return from Interrupt SP  SP+2
4 reti

PC  @ SP
SP  SP+2

No operation
5 nop
( consumes single cycle )
JUMP Instructions

1 jmp label Unconditional Jump

2 jc / jlo label Jump if carry / Jump if lower Jump if C =1

3 jnc / jhs label Jump if not carry / Jump higher or same Jump if C =0

4 Jz / jeq label Jump if zero / Jump if equal Jump if Z =1

5 Jnz / jne label Jump if not zero / Jump if not equal Jump if Z =0

6 jn label Jumpif negative Jump if N =1

7 jge label Jump if greater or equal (signed values) Jump if (N xor V) =0

8 jl label Jump if less than (signed values) Jump if (N xor V) =1

Sample Embedded system on MSP430

MPMC Unit-3

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UNIT – 1

Supports lesser number of instructions. Supports greater number of instructions.

Single, fixed length instructions Variable length instructions

More silicon usage since more additional decoder logic is required to

Because of large amount of different and complex instructions, the design

Comparatively high cost Low cost

I/O devices are mapped into the

• MAIN CHARACTERISTICS OF MSP430 MICROCONTROLLER

• Flash (or) ROM-based low-power MCUs

• Other integrated peripherals:

VARIANT OF FAMILY POWER SPECIFICATIONS DEVICE PARAMETERS OTHER INTEGRATED PERIPHERALS

There are 16 registers

• C : Carry Flag Z : Zero Flag

Register Addressing mode Constant

• Each instruction has 2- parts:

• There are three core-instruction formats:

• The instructions can be classified as follows:

Copies data from source to destination mov.w R5, R6

Push data onto stack push.w R5

Pop data from stack push.w R6

dst = @SP + + SP  SP+2

Add the content of source to destination

Add with carry

Add carry bit to the destination

Subtract the content of source from destination

Subtract with borrow

Subtract borrow bit from the destination

Compares source and destination.

Performs ( dst – src), but Only flags are changed

Clear destination clr.w R6

The content of destination is decremented by 1 dec.w R6

The content of destination is inccremented by 1 inc.w R6

Test ( compare with zero)

Performs ( dst – 0), but Only flags are changed

Instruction Operation Example

Performs the decimal addition of destination and carry. dadc.w R6

Logic Instructions with ONE operand

Instruction Operation Example

1 inv.w dst Performs bit-wise NOT operation (1’s complement) inv.w R6

Instruction Operation Example

Performs bit-wise logic AND operation

Performs bit-wise logic Ex-OR operation

Performs bit-wise Test operation

Set bits in destination

dst  dst OR src

Clear bits in destination

dst  dst AND ~src

Instruction Operation Example

Swap upper and lower bytes

Extend sign of lower byte

Instruction Operation Flag affected

1 clrc Clear Carry bit C=0

2 clrn Clear Negative bit N=0

3 clrz Clear Zero bit Z=0

4 setc Set Carry bit C=1

5 setn Set Negative bit N=1

6 setz Set Zero bit Z=1

7 dint Disable General Interrupts GIE = 0

8 eint Enable Generalwww.maheshelectronics.wordpress.com

rla dst Arithmetic shift Left

rra dst Arithmetic shift Right

rlc dst Rotate Left through Carry