ADVANCED ARM

PROCESSORS

Ch. S. V. Maruthi Rao

Associate Professor
Department of ECE, S. I. E. T

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 ARM CORTEX
• Greater performance efficiency: allowing more work to be done without increasing the
frequency or power requirements
• Low power consumption: enabling longer battery life, especially critical in portable
products including wireless networking applications
• Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as
quickly as possible and in a known number of cycles
• Improved code density: ensuring that code fits in a small memory footprint
• Ease of use: providing easier programmability and debugging for the growing number
of 8-bit and 16-bit users migrating to 32 bits
• Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit
and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less
than US$1 for the first time
• Wide choice of development tools: from low-cost or free compilers to full-featured
development suites from many development tool vendors
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 ARM Families & Architectures

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 ARM CORTEX

• CORTEX is an advanced microcontroller in ARM family, developed with

ARMV7 architecture
• Sub-divided into 3 families
• ARM CORTEX Ax-Series
• ARM CORTEX Rx-Series
• ARM CORTEX Mx-Series
• X indicates a number that identifies the core

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 ARM CORTEX
• Cortex-A series (Application)
• High performance processors available in single-core and multi-
core variants
• Delivers exceptional performance upto 2GHz + in typical processor
modes
• Support for complex Operating System & user applications
• Applications include smartphones, digital TV, smart books, home
gateways, e-book readers, servers etc.
• Supports ARM, Thumb and Thumb 2 instruction set

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 ARM CORTEX
• Cortex-R series (Real-time)
• High & exceptional performance for real-time applications where
there is need for low power consumption
• High reliability & compatibility with existing systems
• Applications include automotive braking system, powertrains,
Mask storage controller (Disk Drives), Networking & Printing,
Digital cameras etc.
• Supports ARM, Thumb and Thumb 2 instruction sets
• Provides a road map for classic processors to easily port to higher
performance systems

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 ARM CORTEX
• Cortex-M series (Microcontroller)
• Cost-sensitive solutions for deterministic microcontroller
applications where there is need for fast, highly deterministic
interrupt management is coupled with desire for extremely low
gate count and lowest possible power consumption
• Applications include microcontrollers, mixed signal devices, smart
sensors, automotive body electronics and airbags; more recently
IoT
• Divided into 4 sub-groups – M0, M1, M3, M4
• Power consumption of Mx series is in the range of 0.84
DMIPS/MHz to 1.25 DMIPS/ MHz

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 Comparison of CORTEX-A
Processors
ARM Core A5 A7 A8 A9
Year of
2009 2011 2005 2007
Establishment
ARM
ARM V7 ARM V7 ARM V7 ARM V7
Architecture
No. of
13 (Integer)
Instruction 8 8 8
10 (NEON)
Pipeline Stages
ACE AMBA AXI AMBA AXI
AMBA AXI
External APB AMBA APB Debug V7
APB
Interfaces used DFT AMBA ATB Compliant
DFT
MBIST DFT DFT
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 Comparison of CORTEX-R
Processors
ARM Core R4 R5 R6 R7
Year of
2011 2011 2011 2016
Establishment
ARM
ARM V7 ARM V7 ARM V7 ARM V7
Architecture
No. of
Instruction 8 8 11 8
Pipeline Stages
Memory
Harvard Harvard Harvard Harvard
Architecture
Max. Clock
> 1.4 GHz > 1.4 GHz > 1.5 GHz > 1.5 GHz
Frequency
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 Comparison of CORTEX-M
ARM Core M0 Processors
M1 M3 M4 M7
Year of
2009 2007 2004 2010 2014
Establishment
ARM Architecture ARM V6M ARM V6M ARM V7M ARM V7E-M ARM V7E-M
No. of Instruction
3 3 3 3 6
Pipeline Stages
Memory
Von-Neuman Von-Neuman Harvard Harvard Harvard
Architecture
1 to 240 1 to 240
Interrupts 1 to 3 (NMI) 1 to 32 (NMI) 1 to 240 (NMI)
(NMI) (NMI)
23 for NMI
Interrupt Latency 16 Cycles 12 Cycles 12 Cycles 12 Cycles
26 for IRQ
Toshiba Tx100 NXP LPC 1300
Xilinx Spartan 3 Toshiba X4 Microchip SAME 70
Microcontroller NXP LPC 1100
Altera Cyclone II
Toshiba TX 03
NXP V3 NXP
chips14/04/20
based on Cypress 4M Actel Smart
IGLOO / E and Microcontrollers
Microprocessors Cypress PSOC 6 Kinetics 10
KV5X
PSOC 4 Fusion
 Harvard vs Von-Neuman
Harvard Von-Neuman
1. Separate buses for instruction 1. Single shared bus for instruction and
and data fetching data fetching
2. Easy to pipeline; so higher 2. Low performance compared to
performance can be achieved Harvard
3. Comparatively high cost 3. Cheaper
4. No Memory Alignment problems 4. Allows self modifying codes
5. No chances of accidental 5. Chances of corruption of program
corruption of program memory as memory as both program and data
data and program memory are memory are physically in the same chip
both physically at different
locations
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 ARM CORTEX ARCHITECTURE
• Harvard bus architecture – 3-stage pipeline with branch speculation
• Configurable nested vectored interrupt controller (NVIC)
• Wake-up Interrupt Controller (WIC) – Enables ultra low-power standby operation
• Extended configurability of debug and trace capabilities – More flexibility for
meeting specific market requirements
• Optional components for specific market requirementss.
• – Memory Protection Unit (MPU)
• – Embedded Trace Macro cell™(ETM™)
• Support for fault robust implementations via configurable observation interface
– EC61508 standard SIL3 certification
• Physical IP support – Power Management Kit™(PMK) + low-power standard cell
libraries and memories enable0.18μm Ultra-Low Leakage (ULL) process

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 ARM CORTEX ARCHITECTURE
• 32 bit addressing supporting 4GB memory space
• 32 bit registers; 32 bit internal data path and 32 bit bus interface unit
• On-chip bus interfaces based on ARM AMBA (Advanced Microcontroller Bus
Architecture)
• Supports up to 240 interrupt requests 8 to 256 interrupt priority levels
• Support for various features of OS implementation such as System Tic Timer,
shadowed stack pointer etc.
• Sleep Mode support and various lower features
• Thumb ISA (Instruction Set Architecture) – Specially Thumb 2
• No need to specify ARM state or Thumb state
• Register file is similar to ARM but with reduced area
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 ARM CORTEX ARCHITECTURE

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 ARM CORTEX ARCHITECTURE
• Nested Vectored Interrupt Controller
• Faster Interrupt Response with less software effort
• 12 cycles, deterministic and low latency
• ISRs are standard C function
• NVIC handles
• Saving corruptible Registers
• Exception Prioritization
• Exception Nesting
• Memory Protection Unit (Optional)
• Has eight memory regions
• Sub region disable, enabling efficient use of memory regions
• Ability to enable a background region that implements the default memory map
attributes

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 ARM CORTEX ARCHITECTURE
• Wake Up Interrupt Controller (WIC) – Optional
• Allows processor to be powered down and powered up when requested
• Enables mw power consumption in deep sleep mode with instant wake up
• Cortex – M supports Sleep Mode and Deep Sleep Mode
• Enter sleep mode using WFI / WFE instruction or “Sleep on Exit” interrupt handling
• Cortex supports two modes
• Normal Program – Thumb state – Running Program code
• Exception handler – Debug state – when processor is halted
• Cortex has two security levels
• Basic Security Model – Access all resources in the processor
• Memory access Protection – Few memory regions and few operations not available
• Cortex processors do not come with memories included
• Program Memory – Flash; Data Memory – SRAM; Peripherals

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 ARM CORTEX ARCHITECTURE
• Floating Point Unit (FPU) – Optional
• 32 dedicated 32 bit instructions for single precision data processing
• Combined multiply and accumulate instructions for increased precision
• Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division and square root
• Decoupled 3 stage pipeline
• Low Cost Debug Sub System – Optional
• Debug access to all registers and memory including access to memory mapped
devices, internal core registers
• Embedded Trace Macro Cell (ETM) – For instruction trace
• Trace Interface unit (TIU) – For bridging to a trace port analyser
• Instrumentation Trace Macro Cell (ITM) – Support for Print & Style debugging
• Data Watch point and Trace (DWT) – To implement watch point, data trace etc.
• Flash Patch and Break Point (FPB) – Implement Break Points and Patches
• Serial wire Debug / JTAG Debug Port – Debug Access
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 ARM
• Bus Interface
CORTEX ARCHITECTURE
• Processor contains 4 AHB (Advanced High Performance Bus) Lite Bus Interfaces
• Private Peripheral Bus (PPB)
• Data and debug access to external PPB space (0xE0040000 to 0xE00FFFFF) are
performed over APB (Advanced Peripheral Bus)
• Trace Port Interface unit and vendor specific peripherals are on the bus
• Core data accesses have higher priority than debug access
• Only address bits necessary to decode the external PPB are supported on this interface
• ETM Interface
• Simple connection of ETM to the processor
• Provides a channel for instruction trace to ETM
• AHB Trace Macro Cell Interface
• Enables connection of AHB trace macro cell to processor
• Provides channel for Data Trace to ETM

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 ARM CORTEX ARCHITECTURE
• Debug Port AHB-AP Interface
• Processor contains AHB-AP interface for debug accesses through an external debug
port
• Serial wire JTAG debug port is a standard core sight debug port that combines JTAG-
DP and SW-DP
• I-Code Memory Interface
• Instruction fetches from code memory space 0x00000000 to 0x1FFFFFFF and
performed over a 32 bit bus
• Debugger cannot access this interface
• All fetches are word wide
• No. of instructions fetched per word depends on the word running and alignment of
code in memory

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 ARM CORTEX ARCHITECTURE
• D-Code Memory Interface
• Data and Debug access to code memory space 0x00000000 to 0x1FFFFFFF and
performed over a 32 bit bus
• Core data has priority over debug accesses
• Control logic in this interface converts unaligned data and debug access to two or three
aligned access depending on size and alignment of unaligned access
• D-Code has higher priority than I-Code
• System Interface
• Instruction fetches, data and debug accesses to address ranges 0x20000000 to
0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF are performed over this bus
• The order in decreasing priority for accessing this bus is
• Data Accesses
• Instruction and Vector Fetches
• Debug
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 What’s OMAP?

OMAPTM (Open Mobile Application Processor)

A Platform comprised of high-performance, power efficient processors,
a robust software infrastructure and comprehensive support network
for the rapid development of differentiated internet appliances, 2.5G
and 3G wireless handsets and PDAs, and other multimedia-enhanced
devices

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 What’s OMAP?

ARM core
DSP/BIOS
C55 core
Symbian, WinCE, etc

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 Feature groups, families or
generations of the OMAP series
• OMAP-DM2xx/OMAP-DM500 comes with 1x ARM7 core (& C54x DSP core
for DM270 only)
• OMAP-DM5xx comes with 1x ARM9 core
• OMAP3xx comes with 1x ARM9 core
• OMAP1 comes with 1x ARM9 core & 1x C55x DSP core
• OMAP L-1x comes with 1x ARM9 core & 1x C674x DSP core
• OMAP2 comes with 1x ARM11 core
• OMAP3 comes with 1x ARM Cortex-A8 core
• OMAP4 comes with 1x ARM Cortex-A9 dual core
• OMAP5 comes with 1x ARM Cortex-A15 dual core
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 OMAP Features

• It seamlessly integrates a software infrastructure, an ARM™ RISC

processor, a high performance, ultra-low-power TI TMS320C55x™
generation digital signal processor (DSP) and shared memory
architecture on the same piece of silicon
• The OMAP software infrastructure includes support for advanced
operating systems and applications through standard APIs
• TI’s unique DSP/BIOS™ Bridge allows the developer to optimally
partition tasks between the RISC and the DSP to maximize
performance without sacrificing battery power.

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 OMAP Features
• The OMAP application environment is fully programmable. This
programmability allows wireless device OEMs, independent
developers, and carriers to provide downloadable software upgrades
as standards change or bugs are found.
• Since there is no need to develop new ASIC hardware to implement
changes, OMAP OEMs (Original Equipment Manufacturer) can
respond to changing market conditions much more quickly than many
of their competitors can.
• Because it is an open architecture with a standardized interface, the
OMAP architecture encourages third-party developers to create new
applications or add functionality.
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 OMAP Features
• It also encourages reuse because the standardized interface allows
OEMs to move software easily from one platform to another.
• Because of its Portability feature it simplifies the development
process for equipment makers seeking the broadest possible market.
• Integrating available third-party and OS native tools with TI's user-
friendly Code Composer Studio™ integrated development
environment (IDE) makes complete software development support
available for the OMAP hardware and software architecture
• For OEMs and third-party developers, the fact that the tools eliminate
the need to address the RISC and the DSP independently facilitates
the creation of wireless multimedia applications and helps get them
to market quickly.
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 OMAP Architecture

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 DSP Advantage

• By adding DSP functionality to the basic processing configuration of a

wireless appliance can developers reproduce high-quality, real-time
video within acceptable power consumption limits
• Programmable DSPs, allow developers to implement any available
standard without creating unacceptable battery drain.
• DSPs provide superior power/performance in such applications
because video, like bestof-class audio playback, is fundamentally a
signal-processing task. And DSPs, by design, are optimized specifically
for signal processing and require less power per cycle than RISC

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 DSP Advantage

• DSP requires fewer instructions to implement a math-intensive,

repetitive algorithm, and it carries out more instructions per clock
cycle. The result is faster implementation with vastly less power
consumption.
• By coupling a DSP with a RISC processor in parallel, the OMAP
architecture gives OEMs access to the capabilities of the DSP while also
providing the command and control functions for which RISC
processors are best suited. This approach provides at least two
important benefits: it improves the quality of basic wireless telephony
functions, and it permits true multimedia multitasking on the wireless
appliance.
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 OMAP DSP/BIOS Bridge
• It provides the application software developer a seamless, easy-to-
use interface to the DSP.
• It allows the developer on the RISC to access and control the DSP
runtime environment using a standardized application programming
interface (API).
• From the developer’s perspective, using TI’s Code Composer Studio
IDE makes the OMAP devices appear to behave and respond as
though a single RISC processor alone were handling all functions.
• There is no need for the developer to program for the two processors
independently or to work in the more difficult language environments
sometimes associated with DSPs.
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 OMAP DSP/BIOS Bridge

• Adding a DSP processor, which is ideally suited for these processing-

intensive functions, relieves the concern that the RISC processor will
be overloaded.
• Allocating parallel functions to the two processors greatly reduces the
possibility that an application will halt in mid-execution because the
RISC has diverted processing power to another activity.

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 Open Architecture

• Using the OMAP architecture, OEMs can maintain their investment in

optimized applications for a device using one protocol as they
develop devices using other protocols
• Once an application is developed for OMAP using the standardized
API, it will be compatible with future end equipments based on the
OMAP architecture, maximizing reuse
• TI also aggressively supports Java™ in the OMAP architecture and will
make the DSP/BIOS Bridge API accessible to developers of Java media
players and the applications that make use of these players.

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 Programmability

• Because it is fully programmable, the OMAP hardware and software

architecture allows OEMs to enhance existing systems and to sell new
features without replacing basic hardware.
• End users can simply download software upgrades or completely new
applications as they become available. OEMs can put their innovative
energies into developing fourth and fifth generation equipment to
serve new and emerging markets.
• Rather than building product-specific applications, they can create for
the broad range of OMAP based OEMs and carriers who can, in turn,
offer the new applications as downloadable enhancements.

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 OMAP Device Overview

The OMAP1510 processor is a

unique dual-core architecture
that combines the command
and control capabilities of the
TI-enhanced ARM™ 925
processor with the high-
performance and low power
capabilities of
theTMS320C55x™ DSP core

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