Chapter 5 Memory and

Memory interface
8086 Architecture

Addressing Mode and

Instruction Set

Assembly language
and Programming

Memory and Application

Memory Interfacing
Memory chips and their application
Memory chips and their application
I/O Interface
I/O chips and applications and Application
I/O chips and applications
Processor Memory I/O

Data Bus

Address Bus

Control Bus
 Objectives
• Memory devices and its classification
• Memory architecture
• Pin Function for SRAM and EPROM
• Memory Interface and Applications
• Cache memory
 Key terms
• Address decoder 地址译码器
• Backup mass storage system 海量备份存储系统
• Bidirectional bus 双向总线
• Chip Enabled (CE) 芯片启动
• Electrically Erasable Read-Only Memory(EEPROM) 电可擦除 ROM
• Erasable Programmable Read-Only Memory (EPROM) 可擦除可编程的
ROM
• Flash disk 闪存盘
• Flash memory EPROM 闪存 EPROM
• Floppy disk 软盘
• Memory Interface 存储器接口
• Magnetic disk 磁盘
• Nonvolatile 非易失性
• Output Enable （ OE ） 输出允许
• Programmable Read-Only Memory （ PROM ） 可编程 ROM
• Write Enable （ WE ） 写入允许
5.1 INTRODUCTION
Typical BUS Interface
Multilayer storage network

Register

Cache

Memory

Disc Memory

Tape Memory Optical Disc Memory

Relation between capacity and speed is

shown in pyramidal construction.
• Memory ： store the program and data
 Semiconductor Memory Fundamentals

• Among the most widely used is RAM and ROM.

• Memory capacity
– The number of bits that a semiconductor chip can store is called its
chip capacity (bits or bytes)
• Memory organization
– Each memory chip contains 2x locations where x is the number of
address pins on the chip.
– Each location contains y bits, where y is the number of data pins
on the chip.
– The entire chip can contain 2x × y bits
– Exam memory organization of 4K×4: 212=4096 locations ,each
location holding 4 bits.
• Memory speed (access time)
 Memory types

ROM(Read Only Memory)

ROM is the type of memory that does not lose its contents when
power is turned off. It is also called nonvolatile memory.
PROM(Programmable Memory)
 User programmable(one-time programmable)memory.
 If the information burned into PROM is wrong, it needs to be discarded
since internal fuses are blown permanently.
 Special equipment needed: ROM burner or ROM programmer.
EPROM(Erasable Programmable ROM)2,000 times
 Allows making changes in the contents of PROM after it is burned.
 One can program the memory chip and erase it thousands of times.
 Erasing its contents can take up to 20 minutes; the entire chip is erased.
 All EPROM chips have a window that is used to shine
ultraviolet(UV)radiation to erase its contents.
 Also referred to as UV-EPROM.
 Memory types
– EEPROM(Electrically Erasable ROM) 500,000 times
• Method of erasure is electrical.
• Moreover, one can select which byte to be erased.
• Cost per bit is much higher than for UV-EPROM.
– Flash Memory EPROM
• First, the process of erasure of the entire contents takes less than a
second, or one might say in a flash, hence its name: flash memory
• When flash memory’s contents are erased, the entire device is
erased.
• Even though flash memories are writeable, like EPROMs they find
their widest use in microcomputer systems for storage of firmware.
 Characteristics of ROM
The classification
ROM: Read Only Memory
Mask type memory
Programmable Read Only Memory
Erasable Programmable Read Only
Memory (ERPOM)
Electrically Erasable Programmable
Read Only Memory (EEPROM)
Flash memory
Characteristics of ROM
Does not lost contents when power is
turned off. Nonvolatile memory.
Write data in chip and inerasable
One-time programmable memory.
Allow making changes in the contents
of PROM after it is burned.
Method of erasure is electrical.
Moreover, one can select which byte
to be erased.
It is a specific type of EEPROM that is
erased and programmed in large
blocks.
 RAM types
SRAM(Static RAM)
Storage cells are made of flip-flops and therefore they do not
require refreshing to keep their data.
Cells handling one bit requires 6 or 4 transistors each, which is
too many.
SRAMS are widely used for cache memory and battery-backed
memory systems.
DRAM(Dynamic RAM)
Uses MOS capacitors to store a bit.
Requires constant refreshing due to leakage(every 2ms-4ms)
Advantages: High density(capacity)/Cheaper cost per bit/Lower
power consumption.
Disadvantage: while it is being refreshed, data cannot be
accessed/larger access time/too many pins due to large capacity.
 Characteristics of RAM
RAM(Random Access Memory) infinite times
RAM memory is called volatile memory since cutting off the
power to the IC will mean the loss of data.
Also referred to as R/WM(Read And Write Memory).

Classification of RAM Characteristics

Random Access Memory (RAM)
Static Random Access Memory
(SRAM)
Dynamic Random Access Memory
(DRAM)
Volatile memory since cutting off the
power to the IC will lose the data
Do not require refreshing to keep their
data.
Require constant refreshing to keep
data, cheaper cost per bit and lower
power consumption.
5.3 ARCHITECTURE OF MEMO
RY
 1. Architecture of RAM

• Address input
• Control input
• Data input/output
 Control Input
• CE: Chip enable, logic 0 enable devices used.

• WE: Write enable, logic 0 enable data written

into devices.

• OE: Output enable, logic 0 enable data read

from devices.
 Standard SRAM devices
SRAM Density (bits) Organization
4361 64K 64Kx1
4363 64K 16Kx4
4364 64K 8Kx8
43254 256K 64Kx8
43256A 256K 32Kx8
431000A 1M 128Kx8
577-749 4M 512Kx8
767-5941 16M 2Mx8
 2. Architecture of DRAM

Block diagram of the 2164B DRAM

8-bit address bus
Data inputs
Data outputs
Control Inputs
 Time-multiplexed address
• 16 bits needed for 64K
• 16 bits are divided into two parts
– RAS is set to 0: first part of address
– CAS is set to 0: second part of address
 Standard DRAM devices
DRAM Density (bits) Organization
2164B 64K 64Kx1
21256 256K 256Kx1
21464 256K 64Kx4
421000 1M 1Mx1
424256 1M 256Kx4
44100 4M 4Mx1
44400 4M 1Mx4
44160 4M 256Kx16
416800 16M 8Mx2
416400 16M 4Mx4
416160 16M 1Mx16
 3. Architecture of ROM

Control bus
CE: chip enable, logic 0 for device to be
active
OE: output enable, logic 0 for output data
 Standard EPROM devices
EPROM Density (bits) Capacity (bytes)
2716 16K 2Kx8
2732 32K 4Kx8
27C64 64K 8Kx8
27C128 128K 16Kx8
27C256 256K 32Kx8
27C512 512K 64Kx8
27C010 1M 128Kx8
27C020 2M 256Kx8
27C040 4M 512Kx8
696-3184 8M 8Mx1
714-7632 16M 2Mx8
 EPROM(cont.)
• Erase all data by UV shining from quartz circle
window on the top of chip.
• Program by special programmer.
• An light tight seal should be stick on window after
program
• Each unit storing data is set to 1.
• Program is inputting 0 to some units.
5.4 MEMORY INTERFACE AND
APPLICATIONS
Main contents:
SRAM 、 EPROM link to CPU
Decoder method are applicable to I/O ports also.
 Working mode
• Minmode: System includes only one
microprocessor, all the control signals are
generated by 8086 CPU.

• Maxmode: System includes more than one

microprocessors, the control signals are
generated by 8255 control unit.
 Minmode 8086 Microcomputer system
Vcc
IOR*
8284A CLOCK MN/MX* Vcc
CLK IOW*
Generator Control
READY M/IO*
RES* Signal MEMR*
RESET RD
WR* Generation MEMW*
GND circuit
RDY
DT/R*
DEN*
8086
ADDR
ALE CLK
WAIT GND
G*
STATE
AD0-AD15 LATCH
GENERATOR ADDR/DATA
A16-A19 BHE*
BHE

DATA
DIR
G*
Transceiver
(2)
A0-A9 D0-D7 WE*OE A0-A9 D0-D7 OE*
Chip
2142RAM(4) 2716-EPROM(2) Select
(2) (2) Logic
1K X 8 1K X 8 2K X 8 2K X 8
CSY CSX
2
 Maxmode 8086 Microcomputer system
Vcc
CLK MRDC* MEMR*
8284A CLOCK MN/MX* GND MWTC* MEMW*
CLK S0 * AMWC
Generator S0* 8288 N.C.
READY S * *IORC*
RES* S 1* IOR*
Bus
1
RESET S* 2 S2* IOWC* IOW*
DENcontrollerAIOWC* N.C.
GND DT/R*
ALE INTA* INTA*

8086 Address
STB
CPU
GND
OE*
AD0-AD7 ADDR/DATA Latches
A8-A19

T Data
Vcc OE*
Transceiver
(2)
A0-A9 D0-D7 WE*OD A0-A9 D0-D7 OE*
Chip
2142RAM(4 2716-2PROM(2) Select
(2)
) (2) Logic
1K X 8 1K X 8 2K X 8 2K X 8
CSY CSX
2
ROM Interface
 5.4.1 Memory selection
• Decoding ： Decode an special input code to an
unique effective output.
• Gate circuit can be used as decoding circuit.
• Integrated decoder is widely used.
– 2:4 decoder ： 74LS139
– 3:8 decoder ： 74LS138
– 4:16 decoder ： 74LS154
74LS138 3-line to 8-line decoder
Input Output
A 0 Enable Select
1 G2 G2 G1 C B A 0 1 2 3 4 5 6 7
B B
2 A

C 3 1 X X X X X 1 1 1 1 1 1 1 1
4 X 1 X X X X 1 1 1 1 1 1 1 1

G2A 5 X X 0 X X X 1 1 1 1 1 1 1 1
6
G2B 7
0 0 1 0 0 0 0 1 1 1 1 1 1 1
G1 0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
Useful decoders: 0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
74LS139 2 to 4 decoder
0 0 1 1 0 1 1 1 1 1 1 0 1 1
74LS138 3 to 8 decoder
0 0 1 1 1 0 1 1 1 1 1 1 0 1
74LS154 4 to 16 decoder 0 0 1 1 1 1 1 1 1 1 1 1 1 0
 (1)Fully decoded

• Fully decoded ： All address lines are used to memory

addressing. Include
– On chip decoded ： Low address lines are used to
address memory chip.
– Chip selection decoding ： High address lines are
used to address chip selection.
• Every memory unit address is unique and never
repetition when fully decoded.
• Decoding circuit will be complicate and link lines is
more.
 A13 through A15 select a 2764 Address Bus A0-A12
A16 through A19 enable the decoder
Data Bus O0-O7
F0000-F1FFF 2764
A13 A 0 (8K x 8)
1 F2000-F3FFF EPROM
A14 B F4000-F5FFF
2
A15 C F6000-F7FFF CS
3
F8000-F9FFF CS
4 CS
5 FA000-FBFFF
G2A FC000-FDFFF
CS
G2B 6 CS
A16 FE000-FFFFF CS
G1 7
CS
CS
A17 Address space RD* of 8086
A18 F0000H--FFFFFH
A19 IC+GATE Decoder
 (2)Partial decoding

• Partial decoding ： Just part high address lines are

used to address memory chip.
• Every memory unit will correspond to several
address (address repetition) . An available address
need to select.
• Can simplify decoding circuit.
• Part address space will be wasted.
 Partial Address decoding
• Not all the address lines need to be used (A14—A19 not used).
so FFFF0,3BFF0,07FF0 pr C3FF0 get the same data.
• (+) the purpose is get the job done in minimum hardware.
• (-)Feature expansion of the memory is impossible, and may cause
invalid data reads due to overlapping memory segment reads(a fatal
error).
A0-A12

8KB 8KB
RAM EPROM

CS* CS*
A13
 Partial Address decoding
• Not all the address lines need to be used (A14—A19 not used).
so FFFF0,3BFF0,07FF0 pr C3FF0 get the same data.
• (+) the purpose is get the job done in minimum hardware.
• (-)Feature expansion of the memory is impossible, and may cause
invalid data reads due to overlapping memory segment reads(a fatal
error).
A0-A12

8KB 8KB
RAM EPROM

CS* CS*
A13
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

For decoder (a) To EPROM

A0-A12 A0-A12 A0-A12
8KB 8KB
EPROM EPROM
O0-O7 O0-O7
4000 to 5FFF 6000 to 7FFF D0-D7
CS* OE* CS* OE*
RD*
IO/M*
A13 A13
A14
Partial Address decoding Example:
A19 A18 not used to decode
A19-A15 A14-A12 A11-A0 一个可用地址

1 xx10x 000 All 0—All 1 20000H-20FFFH

2 xx10x 001 All 0—All 1 21000H-21FFFH
3 xx10x 010 All 0—All 1 22000H-22FFFH
4 xx10x 011 All 0—All 1 23000H-23FFFH

2732 ：
32Kbit EPROM
(8K×8)
 Read/Write Control

• OE of chip is linked to system READ

When chip is selected and READ is effective,
memory chip will open and place data onto data
bus.

• WE of chip is linked to system WRITE

When chip is selected and WRITE is effective,
data on bus will be written to memory chip.
 5.4.2 Comprehensive applications of Memory

Example ： Design a ROM extend circuit. ROM

capacity is 32K word, and address start from
00000H. EPROM is 27256.

EPROM 27256: 32Kx8

 Solutions:
• 1. Decide chip number
Because 32Kx16=64Kx8, so No.=64Kx8/(32Kx8)=2
• 2. Address range:
– Two units together for one byte, one as even chip,
one as odd chip. So 32K address needed, so 15
address lines are needed.
A19 A18 A17 A16 A15--------------A0

Minimum Address 0 0 0 0 0------------------0

Maximum Address 0 0 0 0 1------------------1
• 3. Chip selection
• 4. Interface circuit
5. Conclusion
8086CPU EPROM
DB7…0 D7…0 (even)
DB15…8 D7…0 (odd)
RD OE
An…1 An-1..0
A19…n+1+M/IO CS
Example: Design a RAM
extend circuit, and it
capacity is 32K word.
Address start from 10000H
and chip 62256 is selected.
 Solutions:
• 1. Decide chip number
Because 32Kx16=64Kx8, so
No.=64Kx8/(32Kx8)=2
• 2. Address range:
– If same as previous example, it can not satisfy
write requirement as two units share one
address.
A A A A
19 18 A 17 A
16 15-------------- 0
– 64K address is needed, so address line is 16.
Minimum Address 0 0 0 1 0------------------0
Maximum Address 0 0 0 1 1------------------1
• 3. Chip selection
BHE* A0 Selection
0 0 Whole word(16-bits)
0 1 High Byte to/from odd address
1 0 Low Byte to/from even address
1 1 No selection
4. Interface circuit
 5. Conclusion
8086CPU EPROM
DB7…0 D7…0 (even chip)
DB15…8 D7…0 (odd chip)
RD OE
WR WR
An…1 An-1..0
A19…n+1+M/IO#
A0 Even/CS
/CS
/BHE odd/CS
 5.4.3 General principals
• Two kinds of information in memory
– Program steps which are to perform: ROM
– Variable data that it receives or generates from
working on data: RAM
• Choose proper devices and decide address
range
• Design proper circuits
5.5 CACHE MEMORY
Cache in microprocessor system

The different speed between CPU and DRAM.

On-chip cache is used to feed instructions and
data to the CPU.
L1, L2, L3 may exist
 Summary
• Classification of memory
• Architecture of memory
• Memory connection to CPU
– Full and partial addressing decoding
– Applications
• Cache
 Assignments
• 1. What’s the function of CS or CE pin on a
memory component?
• 2. How many address lines are needed for a
128KB memory? For a 2MB memory?
• 3. Give possible address ranges for each
decoder in following Fig. Address lines A0
through A13 are used by memories.