Unit V

Initialization of 80386DX, Debugging and Virtual

8086 Mode

Prepared by
Shikha Agrawal
 Virtual 8086 Mode
• The 80386 supports execution of one or more 8086, 8088,
80186, or 80188 programs in an 80386 protected-mode
environment.
• An 8086 program runs in this environment as part of a V86
(virtual 8086) task. V86 tasks take advantage of the hardware
support of multitasking offered by the protected mode.
• Not only can there be multiple V86 tasks, each one executing
an 8086 program, but V86 tasks can be multi programmed
with other 80386 tasks.
• To execute an 8086 program ,a "virtual machine“ is to be
form. A complete virtual machine consists not only of 80386
hardware but also of systems software. Thus, the emulation
of an 8086 is the result of cooperation between hardware
and software
 Executing 8086 Code
The processor executes in V86 mode when the VM (virtual
machine) bit in the FLAGS register is set. The processor
tests this flag under two general conditions:
1. When loading segment registers to know whether to use
8086-style address formation.
2. When decoding instructions to determine which
instructions are
sensitive to IOPL. Because IOPL field is having different
function than protected mode.

• Except for these two modifications to its normal operations,

the 80386 in V86 mode operated much as in protected
mode.
 Registers and Instructions in V86 mode

The register set available in V86 mode includes all the registers defined for the
8086 plus the new registers introduced by the 80386: FS, GS, debug registers,
control registers, and test registers.
New instructions introduced by 80386.
── LSS, LFS, LGS instructions
── Long-displacement conditional jumps
── Single-bit instructions
── Bit scan
── Double-shift instructions
── Byte set on condition
── Move with sign/zero extension
── Generalized multiply
-PUSHA
-POPA
-String I/O

To access these instructions only 8086 addressing modes can be used.

 Address Formation in Virtual mode
• It forms linear addresses as an 8086 would. It shifts the selector
left by four bits to form a 20-bit base address. The effective
address is extended with four high-order zeros and added to
the base address to create a linear address.
• Because of the possibility of a carry, the resulting linear address
may contain up to 21 significant bits. An 8086 program may
generate linear addresses anywhere in the range 0 to 10FFEFH
(1 MB plus approximately 64 Kbytes) of the task's linear address
space.
• e.g DS=B000H and Offset =5F00H then physical address will be
B000 DS (Base 16 bit)
+ 5F00 offset (16 bit)
B 5F00 physical address (20 bit)
 Structure of a V86 Task

• The VM86 program is incapable of executing a FAR CALL

.
• The Paging hardware allows the execution of several
virtual mode tasks and provide protection.
• Multiple 8086 programs can be simultaneously executed
on virtul machines. A virtual machine consist of
hardware and software that is required to perform a
particular task.
• Each virtual machine has its own 1MB addressing space
and set of processor registers.The 1 MB addressing
space can be located anywhere in the memory. So the
address range of virtual 8086 task is 1 MB.
 Virtual Machine
#1 1 MB
Virtual machine 1 MB
#2 1 MB
Virtual machine
#3 1 MB
.
.
.
1 MB
Virtual machine 1 MB
#N
Each virtual machine
is a separate 8086 Paging mechanism allows
system 1MB space to be
anywhere in 4GB physical
memory

Concept of virtual machine running on 80386

 Paging for V86 Task

• The paging unit allows simultaneous execution of several virtual

tasks and also provide protection.
• All programs are executed at a privilege level 3 .
• Real mode programs are executed at highest privilege level 0.
• Each VM86 program can be kept in a separate TSS and assign
different set of page tables, that can be mapped anywhere
within the 4 GB physical space.
• Segment register is shifted 4 bits left and added with 16 bit
offset.
• Thus , paging mechanism supports 8086
operating system to share the code between
multiple 8086 applications.
• To protect memory page level protection can be
used.
• The segment level protection is not available in
VM86 mode.
• Figure 15-2 summarizes the ways that the processor can
enter and leave an 8086 program. The processor can enter
V86 by either of two means:
• 1. A task switch to an 80386 task loads the image of
EFLAGS from the new TSS. A value of one in the VM bit of
the new EFLAGS indicates that the new task is executing
8086 instructions; therefore, while loading the segment
registers from the TSS, the processor forms base
addresses as the 8086 would.
• 2. An IRET from a procedure of an 80386 task loads the
image of EFLAGS from the stack. A value of one in VM in
this case indicates that the procedure to which control is
being returned is 8086 procedure.
The CPL at the time the IRET is executed must be zero, else
the processor does not change VM.
The processor leaves V86 mode when an interrupt or exception
occurs. There are two cases:
1. The interrupt or exception causes a task switch. A task switch
from a V86 task to any other task loads EFLAGS from the TSS of the
new task. If the new TSS is an 80386 TSS and the VM bit in the EFLAGS
image is zero TSS, loads the segment registers from the new TSS using
80386-style address formation, and begins executing the instructions
of the new task according to 80386 protected-mode semantics.
2. The interrupt or exception vectors to a privilege-level zero
procedure. The processor stores the current setting of EFLAGS on the
stack, then clears the VM bit. The interrupt or exception handler,
therefore, executes as "native" 80386 protected-mode code. If an
interrupt or exception vectors to a conforming segment or to a
privilege level other than three, the processor causes a
general-protection exception.
Parameter Real Mode Protected Mode Virtual Mode
General It is default When a processor is powerd In the 80386 and
address mode on, it begins execution in real later processor
on Reset mode to maintain backward VM86 mode exist.
compatibility with earlier x86 If the VM bit in the
processors. Protected mode flag register is set,
only be entered after the the processor enters
system software sets up the virtual mode.
several descriptor
tables,enable protection
bit(PE) in CR0.
Use It is the default It allows system software to It allows the
operating mode utilize features such as virtual execution of real
on Reset. Its memory,segmentation,pagin mode applications
main function is g,multi-tasking,protection that are incapable
to initialize and other features designed of running directly
80386 for to increase an operating in protected mode
protected mode system’s control over while the processor
operation. application software. is running a
protected mode
operating system.
Memory addressing In the real mode Can access 4 GB Similar to real
80386 can directly memory with 32 bit mode,The virtual
address upto 1 MB of addressing. mode can access 1
memory MB with 20 bit
physical address.

Entering the mode Enter in real mode on Enter in protected If the VM bit in Eflags
power up or reset mode,when PE bit of register is set,
CR0 register set processor enter in
virtual mode.
Leaving the mode To leave the real Whenever processor The 80386 leaves the
mode and enter into wants to return to virtual mode when
protected mode the real mode the user an interrupt or
PE bit of CR0 must be can clear the PE bit in exception occurs.
set. CR0.

Access In the real mode In the protected In the virtual mode

80386 can access all mode all general all the registers that
the registers. purpose registers, can be accessed by
control registers , the 8086 can be
debug registers, test accessed. The control
registers registers ,test
registers and debug
registers are not
accessible from
VM86 program.