КНУ ім.Т.Г.

Шевченка ФІТ кафедра ПСТ

Computer Architecture Архітектура комп’ютерів

Змістовий модуль 1. Базові поняття

Тема 1. Історія, перспективи комп’ютерів та їх архітектури
Тема 2. Огляд архітектури та екзоархітектури комп’ютерів
Тема 3. Системи числення комп’ютерів
Тема 4. Базові логічні елементи 5 ECTS х 30 = 150 год
Тема 5. Булева алгебра 12Лк = 24 год
Тема 6. Логічні елементи та багаторівнева логіка 13ПЗ = 26 год
  СРС = 100 год
МК1 + МК2 .
Змістовий модуль 2. Функціональний рівень Іспит .
Тема 7. Послідовна логіка (тригери)
Тема 8. Кінцеві автомати Мура і Мілі. Динамічна дисципліна.
Тема 9. Цифрові фунціональні вузли – послідовні елементи
Тема 10. Цифрові фунціональні вузли – матричні елементи
Тема 11. Мікроархітектура (процесори, асемблер)
Тема 12. Ієрархія пам’яті і підсистема вводу виводу
 КНУ ім.Т.Г.Шевченка ФІТ кафедра ПСТ
Computer Architecture
Архітектура комп’ютерів

Змістовий модуль 2. Функціональний рівень

Тема 10. Цифрові фунціональні вузли –

матричні елементи

Topic 10. Digital Functional Array Elements

професор Шевченко Віктор Леонідович

pr. Victor L. Shevchenko
DIGITAL BUILDING BLOCKS Shifters
• Logical shifter: shifts value to left or right and
fills empty spaces with 0’s
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100
• Arithmetic shifter: same as logical shifter, but on right shift,
fills empty spaces with the old most significant bit (msb).
– Ex: 11001 >>> 2 = 11110
– Ex: 11001 <<< 2 = 00100
• Rotator: rotates bits in a circle, such that
bits shifted off one end are shifted into the other end
– Ex: 11001 ROR 2 = 01110
– Ex: 11001 ROL 2 = 00111
Chapter 5 <3>
 A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01

shamt1:0 10
Y3
2 11

A3:0 4 >> 4 Y3:0 00

S1:0
01

10
Y2
11

A <<<<< або >>>>> 0 00

01
S1:0

10
Y1
11

00
S1:0
01

10
Y0
11

Chapter 5 <4>
 A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01

shamt1:0 Y3
10
0
2 11

A3:0 4 >> 4 Y3:0 00

S1:0
01

10
Y2
11

A <<<<< або >>>>> 1 00

01
S1:0

10
Y1
11

00
S1:0
01

10
Y0
11

Chapter 5 <5>
 A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01

shamt1:0 Y3
10
0
2 11

A3:0 4 >> 4 Y3:0 00

S1:0
01

10
Y2 0
11

A <<<<< або >>>>> 2 00

01
S1:0

10
Y1
11

00
S1:0
01

10
Y0
11

Chapter 5 <6>
 A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01

shamt1:0 Y3
10
0
2 11

A3:0 4 >> 4 Y3:0 00

S1:0
01

10
Y2 0
11

A <<<<< або >>>>> 3 00

01
S1:0
Y1
10 0
11

00
S1:0
01

10
Y0
11

Chapter 5 <7>
 A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01

shamt1:0 10
Y3
2 11

A3:0 4 >> 4 Y3:0 00

S1:0
01

10
Y2
11

00
S1:0
01
Y1
• Logical shifter: 10

11
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100 00
S1:0
01

10
Y0
11

Chapter 5 <8>
DIGITAL BUILDING BLOCKS Shifters as Multipliers, Dividers

• A << N = A × 2N
– Example: 00001 << 2 = 00100 (1 × 22 = 4)
– Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
– Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
– Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)

Chapter 5 <9>
DIGITAL BUILDING BLOCKS Multipliers
• Partial products formed by multiplying a single
digit of the multiplier with multiplicand
• Shifted partial products summed to form result
Decimal Binary
230 multiplicand 0101
x 42 multiplier x 0111
460 partial 0101
+ 920 products 0101
9660 0101
+ 0000
result 0100011

230 x 42 = 9660 5 x 7 = 35

Chapter 5 <10>
 A B
DIGITAL BUILDING BLOCKS 4 x 4 Multiplier 4 4

0101
x
x 0111
8
0101
0101 P
0101
+ 0000
0100011 A3 A2 A1 A0

B0
B1
0

A3 A2 A1 A0 0
x B3 B2 B1 B0 B2
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1 0
B3
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0

Chapter 5 <11>
DIGITAL BUILDING BLOCKS 4 x 4 Divider
0 B3 0 B2 0 B1 A3 B0
Legend
R B
1 R B
Cout Cin Cout Cin
+
Q3 D
D
N R'
A2

0
N
1
R'
Q2 A/B = Q + R/B
A1 Algorithm:
1
R’ = 0
for i = N-1 to 0
Q1
R = {R’ << 1. Ai}
A0
D=R-B
1
if D < 0, Qi=0, R’=R
Q0
R3 R2 R1 R0
else Qi=1, R’=D
R’=R
Chapter 5 <12>
Divider
DIGITAL BUILDING BLOCKS Q N = A N / BN Start

AN = aN-1 aN-2 … a1 a0
BN = bN-1 bN-2 … b 1 b0
i = N-1,0

R=A-B
Stop
R >=0

QN = QN-1:0 Qi = 1 Qi = 0

A=R A=A

Chapter 5 <13>
DIGITAL BUILDING BLOCKS Number Systems
• Numbers we can represent using binary
representations
– Positive numbers
• Unsigned binary
– Negative numbers
• Two’s complement
• Sign/magnitude numbers

Numbers with Fractions

• Two common notations:
– Fixed-point: binary point fixed
– Floating-point: binary point floats to the right of the
most significant 1 Chapter 5 <14>
DIGITAL BUILDING BLOCKS Fixed-Point Numbers
• 6.75 using 4 integer bits and 4 fraction bits:
0110 1100
22+21+2-1+2-2 = 6.75
• Binary point is implied
• The number of integer and fraction bits
must be agreed upon beforehand
Example
• Represent 7.510 using 4 integer bits and 4
fraction bits.
7.5
01111000
Chapter 5 <15>
DIGITAL BUILDING BLOCKS Signed Fixed-Point Numbers
• Representations: Example:
– Sign/magnitude Represent -7.510

1111 1000
using 4 integer and
– Two’s complement 4 fraction bits

1. +7.5: 0111 1000

2. Invert bits: 1000 0111
3. Add 1 to lsb: + 1
1000 1000

Chapter 5 <16>
Floating-Point Numbers
DIGITAL BUILDING BLOCKS
• Binary point floats to the right of the most significant 1
• Similar to decimal scientific notation For example:
27310 = 2.73 × 102 ± M × BE In general B=10 (base)

Floating-Point Precision
• Single-Precision: 32-bit
Sign E=2 (exponent) M=2.73 (mantissa)
1 bit 8 bits 23 bits

– 1 sign bit, 8 exponent bits, 23 fraction bits

– bias = 127 (a la shift)
• Double-Precision: 64-bit
– 1 sign bit, 11 exponent bits, 52 fraction bits
– bias = 1023
Chapter 5 <17>
Floating-Point Representation 1
DIGITAL BUILDING BLOCKS
• Example: represent the 22810 as a 32-bit floating point representation
We show three versions –final version is called the IEEE 754
floating-point standard
1. Convert decimal to binary (don’t reverse steps 1 & 2!):
+ 22810 = 111001002

2. Write the number in “binary scientific notation”:

111001002 = 1.110012 × 27

3. Fill in each field of the 32-bit floating point number:

1 bit 8 bits 23 bits

0 00000111 11 1001 0000 0000 0000 0000
Sign Exponent Mantissa
Chapter 5 <18>
Floating-Point Representation 1
DIGITAL BUILDING BLOCKS
1 bit 8 bits 23 bits
0 00000111 11 1001 0000 0000 0000 0000
Sign Exponent Mantissa

• First bit of the mantissa is always 1:

– 22810 = 111001002 = 1.11001 × 27

• So, no need to store it: implicit leading 1

• Store just fraction bits in 23-bit field

Floating-Point Representation 2
1 bit 8 bits 23 bits
0 00000111 110 0100 0000 0000 0000 0000
Sign Exponent Fraction
Chapter 5 <19>
DIGITAL BUILDING BLOCKS Floating-Point Representation 3
• Biased exponent: bias = 127 (011111112)
– Biased exponent = bias + exponent
– Exponent of 7 is stored as:
127 + 7 = 134 = 0x100001102

• The IEEE 754 32-bit floating-point representation of 22810

1 bit 8 bits 23 bits

0 10000110 110 0100 0000 0000 0000 0000
Sign Biased Fraction
Exponent

Chapter 5 <20>
DIGITAL BUILDING BLOCKS Floating-Point Example
Write -58.2510 in floating point (IEEE 754)
1. Convert decimal to binary:
58.2510 = 111010.012

2. Write in binary scientific notation:

1.1101001 × 25
3. Fill in fields:
Sign bit: 1 (negative)
8 exponent bits: (127 + 5) = 132 = 100001002
23 fraction bits: 110 1001 0000 0000 0000 0000
1 bit 8 bits 23 bits
1 100 0010 0 110 1001 0000 0000 0000 0000
Sign Exponent Fraction
in hexadecimal: 0xC2690000

Chapter 5 <21>
DIGITAL BUILDING BLOCKS Floating-Point: Special Cases
Number Sign Exponent Fraction
0 X 00000000 00000000000000000000000
∞ 0 11111111 00000000000000000000000
-∞ 1 11111111 00000000000000000000000
NaN X 11111111 non-zero
• Overflow: number too large to be represented
• Underflow: number too small to be represented
• Rounding modes:
Example: 1.100101 (1.578125) to only 3 fraction bits
– Down: 1.100
– Up: 1.101
– Toward zero: 1.100
– To nearest: 1.101 (1.625 is closer to 1.578125 than 1.5 is)
Chapter 5 <22>
DIGITAL BUILDING BLOCKS Floating-Point Addition
1. Extract exponent and fraction bits
2. Prepend leading 1 to form mantissa
3. Compare exponents
4. Shift smaller mantissa if necessary
5. Add mantissas
6. Normalize mantissa and adjust exponent if necessary
7. Round result
8. Assemble exponent and fraction back into floating-point
format

Chapter 5 <23>
DIGITAL BUILDING BLOCKS Floating-Point Addition Example
Add the following floating-point numbers:
0x3FC00000
0x40500000
1. Extract exponent and fraction bits
1 bit 8 bits 23 bits
0 01111111 100 0000 0000 0000 0000 0000
Sign Exponent Fraction
1 bit 8 bits 23 bits
0 10000000 101 0000 0000 0000 0000 0000
Sign Exponent Fraction

For first number (N1): S = 0, E = 127, F = .1

For second number (N2): S = 0, E = 128, F = .101

2. Prepend leading 1 to form mantissa

N1: 1.1
N2: 1.101 Chapter 5 <24>
DIGITAL BUILDING BLOCKS Floating-Point Addition Example
3. Compare exponents
127 – 128 = -1, so shift N1 right by 1 bit

4. Shift smaller mantissa if necessary

(N1): S = 0, E = 127, F = .1 new N1: 1.1
(N2): S = 0, E = 128, F = .101 new N2: 1.101

shift N1’s mantissa: 1.1 >> 1 = 0.11 (× 21)

5. Add mantissas
0.11 × 21
+ 1.101 × 21
10.011 × 21
Chapter 5 <25>
DIGITAL BUILDING BLOCKS Floating Point Addition Example
6. Normalize mantissa and adjust exponent if necessary
10.011 × 21 = 1.0011 × 22
7. Round result
No need (fits in 23 bits)
8. Assemble exponent and fraction back into floating-point
format
S = 0, E = 2 + 127 = 129 = 100000012, F = 001100..
1 bit 8 bits 23 bits
0 10000001 001 1000 0000 0000 0000 0000
Sign Exponent Fraction
in hexadecimal: 0x40980000

Chapter 5 <26>
DIGITAL BUILDING BLOCKS Counters
• Increments on each clock edge
• Used to cycle through numbers. For example,
– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…
• Example uses:
– Digital clock displays
– Program counter: keeps track of current instruction executing

Symbol Implementation

CLK
N CLK
N N
+ Q
Q N N r
1
Reset
Reset

Chapter 5 <27>
DIGITAL BUILDING BLOCKS Shift Registers
• Shift a new bit in on each clock edge
• Shift a bit out on each clock edge
• Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)

Symbol: Implementation:
CLK
N
Q Sin Sout

Sin Sout
Q0 Q1 Q2 QN-1

Chapter 5 <28>
DIGITAL BUILDING BLOCKS Shift Register with Parallel Load
• When Load = 1, acts as a normal N-bit register
• When Load = 0, acts as a shift register
• Now can act as a serial-to-parallel converter (Sin to Q0:N-1) or
a parallel-to-serial converter (D0:N-1 to Sout)

D0 D1 D2 DN-1
Load
Clk
Sin 0 0 0 0 Sout
1 1 1 1

Q0 Q1 Q2 QN-1

Chapter 5 <29>
Memory Arrays
DIGITAL BUILDING BLOCKS N
Address Array
• Efficiently store large amounts of data
• 2-dimensional array of bit cells
• Each bit cell stores one bit M
• M-bit data value read/ written at each
Data
unique N-bit address:
– 2N rows and M columns
– Depth: number of rows (number of words)
– Width: number of columns (size of word)
– Array size: depth × width = 2N × M Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
• 22 × 3-bit array
3 00 0 1 1
• Number of words: 4
• Word size: 3-bits Data width
• For example, the 3-bit word stored at address 10 is 100
Chapter 5 <30>
Memory Array Bit Cells
DIGITAL BUILDING BLOCKS 10
1024-word x
Address 32-bit
bitline = 0 bitline = Z Array
wordline = 1 wordline = 0
stored stored
bit = 0 bit = 0
32
bitline = 1 bitline = Z
wordline = 1 wordline = 0 Data
stored stored
bit = 1 bit = 1

(a) (b)

2:4
Decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
Wordline: wordline1 bit = 1 bit = 0 bit = 0
01
• like an enable stored stored stored
bit = 1 bit = 1 bit = 0
• corresponds to unique address 00
wordline0

• only one wordline HIGH at once stored

bit = 0
stored
bit = 1
stored
bit = 1

• single row in memory array read/written Chapter 5 <31> Data2 Data1 Data0
Types of Memory
DIGITAL BUILDING BLOCKS
RAM (Random Access Memory): volatile
random (in contrast to sequential access such as a tape recorder)
• Read and written quickly
bitline
• Main memory in computer is RAM (DRAM) wordline

• DRAM (Dynamic RAM)

uses a capacitor
• SRAM (Static RAM) bitline bitline
wordline
uses cross-coupled inverters

ROM (Read Only Memory): nonvolatile

Now it is NOT Read Only (but name remain)
• Read quickly, but writing is impossible or slow
• Flash memory in cameras, thumb drives, and digital cameras are all ROMs
Chapter 5 <32>
DRAM
DIGITAL BUILDING BLOCKS Robert Dennard, 1932 -
• Invented in 1966 at IBM
• Others were skeptical that the idea would work
• By the mid-1970’s DRAM in virtually all computers

• Data bits stored on capacitor

• Dynamic because the value needs to be refreshed
(rewritten) periodically and after read:
– Charge leakage from the capacitor degrades the value
– Reading destroys the stored value
bitline bitline
wordline wordline

stored + + stored
bit = 1 bit = 0
Chapter 5 <33>
 DIGITAL BUILDING BLOCKS
DDR
SDRAM

Chapter 5 <34>
DDR SDRAM
DIGITAL BUILDING BLOCKS
Максимальная
теоретическая
пропускная
Тактовспособность, МБ/с
ая
Названи частот
Тип
е чипа а
модуля шины однока
памят нальны двухкана
и, МГц й льный
режим режим

PC1600* DDR200 100 1600 3200

PC2100* DDR266 133 2133 4267
PC2400 DDR300 150 2400 4800
PC2700* DDR333 166 2667 5333
PC3200* DDR400 200 3200 6400
PC3500 DDR433 217 3467 6933
PC3700 DDR466 233 3733 7467
PC4000 DDR500 250 4000 8000
PC4200 DDR533 267 4267 8533
PC5600 DDR700 350 5600 11200 Chapter 5 <35>
DDR3 SDRAM
DIGITAL BUILDING BLOCKS

Частот Частот Эффективная Пиковая скорость передачи

Время данных при 64-битной
Стандартно а а (удвоенная) Название
цикла, шине данных в
е название памят нс шины, скорость, млн. модуля одноканальном режиме,
и, МГц МГц передач/с
МБ/с
DDR3‑800 100 10,00 400 800 PC3‑6400 6400
DDR3‑1066 133 7,50 533 1066 PC3‑8500 8533
DDR3‑1333 166 6,00 667 1333 PC3‑10600 10667
DDR3‑1600 200 5,00 800 1600 PC3‑12800 12800
DDR3‑1866 233 4,29 933 1866 PC3‑14900 14933
DDR3‑2133 266 3,75 1066 2133 PC3‑17000 17066
DDR3‑2400 300 3,33 1200 2400 PC3‑19200 19200
Chapter 5 <36>
Fujio Masuoka, 1944 -
DIGITAL BUILDING BLOCKS
• Developed memories and high speed circuits at
Toshiba, 1971-1994
• Invented Flash memory as an unauthorized project
pursued during nights and weekends in the late
1970’s
• The process of erasing the memory reminded him
of the flash of a camera
• Toshiba slow to commercialize the idea; Intel was
first to market in 1988

Chapter 5 <37>
 DIGITAL BUILDING BLOCKS

Chapter 5 <38>
ROM Logic
DIGITAL BUILDING BLOCKS wordline
bitline

2:4
Decoder bit cell Address Data
containing 0
11 11 0 1 0
2
Address
bitline 10 1 0 0
10 depth
wordline 01 1 1 0
01 bit cell 00 0 1 1
containing 1 A1A0
00 width
A1A0 Data2 Data1 Data0 Logic with Any Memory
2:4
Decoder
wordline
Array bitline bitline2
bitline 1 0

11 3

  stored stored stored

Data2 = A1 A0 Address 2

10
wordline2
bit = 0 bit = 1 bit = 0

stored stored stored

wordline1 bit = 1 bit = 0 bit = 0

Data1 = A1 + A0 01
stored
bit = 1
stored
bit = 1
stored
bit = 0
wordline0
00
stored stored stored
Data0 = A1A0 bit = 0 bit = 1 bit = 1

Chapter 5 <39> Data2 Data1 Data0

Logic with Memory Arrays
DIGITAL BUILDING BLOCKS
Called lookup tables (LUTs): look up output at each input
combination (address) 4-word x 1-bit Array

2:4
Decoder bitline
Truth
Table 00
stored
A A1
bit = 0
A B Y 01
B A0
0 0 0 stored
0 1 0 bit = 0
1 0 0 10
1 1 1 stored
bit = 0
11
stored
bit = 1

Chapter 5 <40> Y
Example: Logic with Memory Arrays
DIGITAL BUILDING BLOCKS
Implement the following logic functions using a 22 × 3-bit
memory array:
– X = AB
– Y=A+B
– Z=AB

2:4 2:4
Decoder Decoder bitline2 bitline1 bitline0
wordline3
11 11
2 2 stored stored stored
A, B A, B bit = 1 bit = 1 bit = 0
wordline2
10 10
stored stored stored
wordline1 bit = 0 bit = 1 bit = 1
01 01
stored stored stored
bit = 0 bit = 1 bit = 0
wordline0
00 00
stored stored stored
bit = 0 bit = 0 bit = 0
X Y Z
Chapter 5 <41>
X Y Z
DIGITAL BUILDING BLOCKS Multi-ported Memories
• Port: address/data pair
• 3-ported memory
– 2 read ports (A1/RD1, A2/RD2)
– 1 write port (A3/WD3, WE3 enables writing)
• Register file: small multi-ported memory
CLK

WE3
A1 RD1
N M
A2 RD2
N M

A3 Array
N
WD3
M

Chapter 5 <42>
DIGITAL BUILDING BLOCKS SystemVerilog Memory Arrays
// 256 x 3 memory module with one read/write port
module dmem( input logic clk, we,
input logic [7:0] a,
input logic [2:0] wd,
output logic [2:0] rd);

logic [2:0] RAM[255:0];

assign rd = RAM[a];

always @(posedge clk)

if (we)
RAM[a] <= wd;
endmodule

Chapter 5 <43>
DIGITAL BUILDING BLOCKS Logic Arrays
• PLAs (Programmable logic arrays)
– AND array followed by OR array
– Combinational logic only
– Fixed internal connections

• FPGAs (Field programmable gate arrays)

– Array of Logic Elements (LEs)
– Combinational and sequential logic
– Programmable internal connections

Chapter 5 <44>
 PLAs
DIGITAL BUILDING BLOCKS A B C
OR ARRAY

• X = ABC + ABC ABC

• Y = AB ABC
Inputs
M AB

AND Implicants OR
ARRAY N ARRAY
AND ARRAY
X Y

P
Outputs
A B C
OR ARRAY

Dot Notation ABC

ABC

AB

AND ARRAY
Chapter 5 <45> X Y
FPGA: Field Programmable Gate Array
DIGITAL BUILDING BLOCKS
• Composed of: LEs (Logic elements): perform logic
– LUTs (lookup tables): perform
combinational logic
– Flip-flops: perform sequential
General FPGA Layout logic
– Multiplexers: connect LUTs
and flip-flops
– IOEs (Input/output elements):
interface with outside world
– Programmable interconnection:
connect LEs and IOEs
– Some FPGAs include other
building blocks such as multipliers
and RAMsChapter 5 <46>
 • The Altera Cyclone IV LE has:
Altera Cyclone IV LE
DIGITAL BUILDING BLOCKS – 1 four-input LUT
– 1 registered output
– 1 combinational output

Chapter 5 <47>
LE Configuration Example
DIGITAL BUILDING BLOCKS
Show how to configure a Cyclone IV LE to perform the
following functions:
– X = ABC + ABC
– Y = AB
(A) (B) (C) (X)
data 1 data 2 data 3 data 4 LUT output
0 0 0 X 0
0 0 1 X 1
A data 1
0 1 0 X 0
B data 2
0 1 1 X 0 C
data 3 X
1 0 0 X 0
0 data 4
1 0 1 X 0 LUT
1 1 0 X 1
LE 1
1 1 1 X 0

(A) (B) (Y)

data 1 data 2 data 3 data 4 LUT output
0 0 X X 0 A data 1
0 1 X X 0 B data 2
1 0 X X 1 0 data 3 Y
1 1 X X 0 0 data 4 LUT

Chapter 5 <48> LE 2
DIGITAL BUILDING BLOCKS FPGA Design Flow
Using a CAD tool (such as Altera’s Quartus II)
• Enter the design using schematic entry or an HDL
• Simulate the design
• Synthesize design and map it onto FPGA
• Download the configuration onto the FPGA
• Test the design

Chapter 5 <49>
 КНУ ім.Т.Г.Шевченка ФІТ кафедра ПСТ
Computer Architecture Архітектура комп’ютерів

Змістовий модуль 1. Базові поняття

Тема 1. Історія, перспективи комп’ютерів та їх архітектури
Тема 2. Огляд архітектури та екзоархітектури комп’ютерів
Тема 3. Системи числення комп’ютерів
Тема 4. Базові логічні елементи 5 ECTS х 30 = 150 год
Тема 5. Булева алгебра 12Лк = 24 год
Тема 6. Логічні елементи та багаторівнева логіка 13ПЗ = 26 год
  СРС = 100 год
МК1 + МК2 .
Змістовий модуль 2. Функціональний рівень Іспит .
Тема 7. Послідовна логіка (тригери)
Тема 8. Кінцеві автомати Мура і Мілі. Динамічна дисципліна.
Тема 9. Цифрові фунціональні вузли – послідовні елементи
Тема 10. Цифрові фунціональні вузли – матричні елементи
Тема 11. Мікроархітектура (процесори, асемблер)
Тема 12. Ієрархія пам’яті і підсистема вводу виводу
 КНУ ім.Т.Г.Шевченка ФІТ кафедра ПСТ
Computer Architecture
Архітектура комп’ютерів

Змістовий модуль 2. Функціональний рівень

Тема 10. Цифрові фунціональні вузли –

матричні елементи

Topic 10. Digital Functional Array Elements

професор Шевченко Віктор Леонідович

pr. Victor L. Shevchenko