ECE 351

Verilog HDL
Chapter 4: Gate Level Modelling
Netlists
Netlists
Port Connection Rules
Modify module vabc to display the results
Connecting a Driven Net to an output Port
Built-in primitives
Built-in primitives - Single output
Single Input
Tri-State
MOS switches
MOS switches
Single Strength Reduction
The nmos and pmos Switches
Example 2 --- CMOS NAND Gates
Cmos and rcmos switches (transmission gate)
CMOS Switch
An Example --- A 2-to-1 Multiplexer
Pullup and pulldown
Bidirectional switches
Bidirectional switches-Delay Specifications
Gate Delays
Gate Delays
Gate Delays
Gate Delays
Inertial Delays
transport delay
transport delay
Switch-level models
Switch-level models
A Static RAM Model
A Static RAM Model
User-defined primitives
User-defined primitives
UDP Definition
Use
Combinatorial
Combinatorial
Combinatorial
User-defined primitives - Sequential
User-defined primitives - Sequential
Initialization
Example: 4-bit adder
Verilog source
Verilog source
Verilog source
Shift Register
Shift Register
Shift Register – Verilog Source