Digital IC Layout Techniques

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Standard Cells
N Well
VDD Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects

Cell height is “12 pitch”

Out
In
2

Rails ~10
GND
Cell boundary

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Standard Cells
With minimal VDD With silicided VDD
diffusion diffusion
routing

VDD

M2
Out In Out
In
In Out

M1

GND GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Standard Cells
VDD 2-input NAND gate
VDD

B
A B

Out
A

GND

4
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Standard Cell Layout Methodology –
1990s
Mirrored Cell

No Routing VDD
channels
VDD

M2

M3
GND
Mirrored Cell GND

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Two NMOS in Series

Out
A B
A

Out
B

GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Two NMOS in Parallel
Out

A B
Out

A B

GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 PDN of a Complex Gate-1
Out

C
Out B

A
C
B
GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 PDN of a Complex Gate-2 C
B

A Out

Out

A B

GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Multi-Fingered Transistors
One finger Two fingers (folded)

Less diffusion capacitance

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Stick Diagrams
Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Stick Diagrams
Logic Graph X PUN
A
j C
B C

X i VDD
X = C • (A + B)
C
i B j A

A B
PDN
A GND
B
C

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Two Versions of C • (A + B)

A C B A B C

VDD VDD

X X

GND GND

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Consistent Euler Path

X i VDD

B j A

GND A B C

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 OAI22 Logic Graph
X PUN
A C

B D D C

X VDD
X = (A+B)•(C+D)

C D
B A

A B PDN
A GND
B
C
D

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Layout
X PUN

D C

X VDD x

B A VDD

a b c d
PDN
GND
GND

stick diagram for ordering {a b c d}

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Parasitic Capacitance
Mainly three types of parasitic capacitances
exist associated with a design/layout
• Diffusion capacitance
• Gate/poly capacitance
• Interconnect/wire capacitance

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 Parasitic Resistance
Mainly two types of parasitic resistances exist
associated with a design/layout:
(1)Interconnect resistance and
(2)Contact or Via resistance

• Interconnect resistance is calculated from Sheet

Resistance and its length and width.
•
l
w

 l l
R    Rsquare 
t w w

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
 …contd
(2) Contact or Via resistance Rvia

Rvia
Rvia 4

Possible Interconnect square/sheet resistance values:

• Metal 0.2-0.8
• Contacts/vias 5-100

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© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits