MODULE-3

Interrupts And Programming

TOPICS
• Interrupts and interrupt service routines
• Interrupt cycle of 8086
• Non mask able interrupt
• Maskable interrupt(INTR)
• Interrupt programming
• Programmable Interrupt Controller 8259A
INTERRUPTS AND INTERRUPT SERVICE ROUTINES

Interrupt
• An interrupt is the method of processing the microprocessor by peripheral
• device.
• An interrupt is used to cause a temporary halt in the execution of program.
• An INTERRUPT is a condition that causes the microprocessor to temporarily work on a
different task and then return to its previous task.
• Interrupt is an event or signal that request to attention of CPU.
• Whenever an interrupt occurs the processor completes the execution of the current
instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt
Handler.
• ISR is a program that tells the processor what to do when the interrupt occurs. After the
execution of ISR, control returns back to the main routine where it was interrupted.
Interrupt Service Routine
• For every interrupt, there must be an interrupt service routine (ISR), or
interrupt handler.
• When an interrupt is invoked, the microprocessor runs the interrupt service
routine.
• For every interrupt, there is a fixed location in memory that holds the
address of its ISR.
• The group of memory locations set aside to hold the addresses of ISRs is
called the interrupt vector table.
Hardware Interrupts

• Hardware interrupts are those interrupts which are caused by any peripheral
device by sending a signal through a specified pin to the microprocessor.
• There are two hardware interrupts in 8086 microprocessor.They are:
(A) NMI (Non Maskable Interrupt) – It is a single pin non maskable
hardware interrupt which cannot be disabled. It is the highest priority interrupt in
8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt.
IP is loaded from word location 00008 H and CS is loaded from the word location
0000A H.
(B) INTR (Interrupt Request) – It provides a single interrupt request and is
activated by I/O port. This interrupt can be masked or delayed. It is a level triggered
interrupt. It can receive any interrupt type, so the value of IP and CS will change on
the interrupt type received.
Software Interrupts
•These are instructions that are inserted within the program to
generate interrupts.
•There are 256 software interrupts in 8086 microprocessor. The
instructions are of the format INT type where type ranges from 00
to FF.
•The starting address ranges from 00000 H to 003FF H. These are 2
byte instructions. IP is loaded from type * 04 H and CS is loaded
from the next address give by (type * 04) + 02 H.
• Some important software interrupts are:
(A) TYPE 0 corresponds to division by zero(0).
(B) TYPE 1 is used for single step execution for debugging of program.
(C) TYPE 2 represents NMI and is used in power failure conditions.
(D) TYPE 3 represents a break-point interrupt.
(E) TYPE 4 is the overflow interrupt.
INTERRUPT CYCLE OF 8086
There are two types of interrupts:
• External Interrupt: In external interrupt, an external device or a signal
interrupts the processor from outside ie. The output is genertated
outside the processor.
Example: a key board interrupt
• Internal Interrupt: In Internal interrupt , the interrupt is generated
internally.
Example: Zero interrupt, overflow interrupt, interrupts due to
INT instructions.
• Suppose an external device interrupts the CPU at the interrupt pin,
either NMI or INTR of the 8086, while the CPU is executing an
instruction of a program.
• The CPU first completes the execution of the current instruction.The
IP is then incremented to the next instruction.
• The CPU then acknowledges the requesting device on its INTA pin
immediately if it is a NMI,TRAP or Divide by zero interrupt.If it is an
INT request, the CPU checks the IF flag.If the IF is not set, the
interrupt requests are ignored.
• Note that the responses to the NMI ,TRAP and Divide by Zero
interrupt requests are independent of the IF flag.
INTERRUPT RESPONSE SEQUENCE
• After an interrupt is acknowledged , the CPU computes the vector
address from the type of the interrupt that may be passed to the
interrupt structure of the CPU internally (in case of software
interrupts,NMI,TRAP and Divide by Zero interrupts)or externally,
i.e. from an interrupt controller in case of external interrupts.
• The contents of IP and CS are next pushed to the stack.The contents of IP
and CS now point to the address of the next instruction of the main
program from which the execution is to be continued after executing the
ISR.The PSW is also pushed to the stack.
• Interrupt Flag(IF) is cleared. The TF is also cleared ,after every response
to the single step interrupt.
• The control is then transferred to the interrupt service routine for serving
the interrupting device.
• The new address of ISR is found out from the interrupt vector table.The
execution of the ISR starts.
• If further interrupts are to be responded to during the time of the first
interrupt is being serviced, the IF should again be set to 1 by the ISR of
the first interrupt.
• If the interrupt flag is not set ,the subsequent interrupt signals will not be
acknowledged by the processor ,till the current one is completed .
• The programmable interrupt controller is used for managing such
multiple interrupts based on their priorities.
• At the end of ISR the last instruction should be IRET.
• When the CPU executes IRET, the content of flags,IP and CS which were
saved at the start by the CALL instruction are now retrieved to the
respective registers.The execution continues onwards from this address,
received by IP and CS.
How the 8086 finds out the address of an ISR

• Every external and internal interrupt is assigned with a type(N), that is

either implicit or specified in the instruction INT N.
• In case of external interrupts, the type is passed to the processor by
an external hardware like programmable interrupt controller.
• In the zeroth segment of segment of physical address space, I,e
CS=0000,Intel has reserved 1,024 locations for storing the interrupt
vector table.
• The 8086 supports a total of 256 types of the interrupts,i.e from 00 to
FFH.
• Each interrupt requires 4 bytes, i.e.two bytes each for IP and CS of its
ISR.Thus a total of 1,024 bytes are required for 256 interrupt types,
hence the interrupt vector table starts at location 0000:0000 and ends
at 0000:03FFH.
• The interrupt vector table contains the IP and CS of all the interrupt
types store sequentially from address 0000:0000 to 0000:03FFH.
• The interrupt type N is multiplied by 4 and the hexadecimal
multiplication obtained gives the offset address in the zeroth code
segment at which the IP and CS addresses of the interrupt service
routine (ISR) are stored. The execution automatically stars from the
new CS:IP.
NON MASKABLE INTERRUPT(NMI)

• The processor provides a single non-maskable interrupt pin (NMI) which has higher
priority than the maskable interrupt request pin (INTR).
• The NMI is edge-triggered on a LOW-to-HIGH transition.
• The activation of this pin causes a type 2 interrupt.
• NMI is required to have a duration in the HIGH state of greater than two CLK cycles,
but is not required to be synchronized to the clock.
• Any high-going transition of NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves of a block-type instruction.
• Worst case response to NMI would be for multiply, divide, and variable shift
instructions.
• There is no specification on the occurrence of the low-going edge; it may occur
before, during, or after the servicing of NMI.
• Another high-going edge triggers another response if it occurs
after the start of the NMI procedure.
• The signal must be free of logical spikes in general and be free of
bounces on the low-going edge to avoid triggering extraneous
responses.
MASKABLE INTERRUPT(INTR)
• The INTR is a maskable interrupt because the microprocessor
will be interrupted only if interrupts are enabled using set
interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.
• The INTR interrupt is activated by an I/O port. If the interrupt is
enabled and NMI is disabled.
• INTR has lower priority as compared to NMI.
• Priorities within the INTR types are decided by the type of the
INTR signal that is to be passed to the processor via data bus by
some external device like the programmable interrupt
controller.
• The INTR signal is level triggered and can be masked by resetting the
interrupt flag, it is internally synchronized with high transition of the
CLK.
• For the INTR signal to respond in the next instruction cycle,it must go
high in the last clock cycle of the current instruction or before that.
• The INTR requests appearing after the last clock cycle of the current
instruction will be responded to after the execution of next instruction.
• The status of the pending interrupts is checked at the end of each
instruction cycle.
• If IF is set, the processor is ready to respond to any INTR interrupt.
• If IF is reset, the processor will not serve any interrupt.
• These actions are taken by the microprocessor −
- First completes the current instruction.
- Activates INTA output and receives the interrupt type, say X.
- Flag register value, CS value of the return address and IP value of
the return address are pushed on to the stack.
- IP value is loaded from the contents of word location X × 4
- CS is loaded from the contents of the next word location.
- Interrupt flag and trap flag is reset to 0.
• If an external signal interrupts the processor and the pin LOCK’ goes low at
the trailing edge of the first ALE pulse that appears after the interrupt signal
preventing the use of bus for any other purpose.
• The pin LOCK’ remains low till the start of the next machine cycle.
• With the trailing edge of LOCK’ , the INTA’ goes low an remains low for two
clock states before returning back to the high state.
• The first trailing edge of ALE floats the bus AD0-AD7,while the second
trailing edge prepares the bus to accept the type of interrupt.The type of
interrupt remains on the bus for a period of two cycles.
INTERRUPT PROGRAMMING
• While programming for any type of interrupt, the programmer must,
either externally or through the program, set the interrupt vector
table for that type preferably with the CS and IP addresses of the
interrupt service routine.
• The method of defining the interrupt service routine for software as
well as hardware interrupt is the same.
EXECUTION SEQUENCE IN CASE OF A SOFTWARE INTERRUPT
TRANSFER OF CONTROL FOR THE NESTED INTERRUPTS
INTEL 8259A Programmable Interrupt Controller

The 8259A is a programmable interrupt controller specially designed to work with Intel
microprocessor 8080, 8085A, 8086, 8088. The main features of 8259A programmable
interrupt controller are given below:
1) It can handle eight interrupt inputs. This is equivalent to providing eight interrupt
pins on the processor in place of one INTR (in 8085A)/INT(in 8086) pin.
2) The chip can vector an interrupt request anywhere in the memory map from 0000H
to FFFFH in 8085A microprocessor. However, all the eight interrupts are spaced at an
interval of either four or eight locations. This eliminates the major drawback of 8085A
interrupts in which all interrupts are vectored to memory location on page 00H i.e.,
TRAP, RST7.5, RST6.5 and RST5.5 are vectored to memory locations 0024H, 003CH,
0034H and 002CH respectively.
3) It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of
interrupts can be changed under running condition. Some of the desired lower priority
interrupts may be allowed to be acknowledged during the service of higher priority
interrupts.
4) Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5
and RST5.5 interrupts of 8085A.
5) The status of pending interrupts, in service interrupts, and masked interrupts can be
read at any time similar to RST interrupts of 8085A.
6) The chip can be programmed to accept interrupt requests either as level triggered or
edge triggered interrupt request unlike your RST interrupts where some are edge triggered
and some are level triggered. However, all interrupts must be either level triggered or edge
triggered.
7) If required, nine 8259As can be cascaded in a master-slave configuration mode to handle
64 interrupt inputs. In this case, the interrupting devices send their interrupt requests
either to slave 8259A or to master 8259A directly. The slave 8259As send their interrupt to
master interrupt request inputs and the master will send a single interrupt to
microprocessor interrupt pin INTR/INT.
• The 8259 A is contained in a 28 dual-in-line package that requires only +5V supply
voltage. The 8259A is upward compatible with 8259. The main difference between the
two is that the 8259A can be used with Intel 8086/8088 processor. It also includes
additional features such as level triggered mode, buffered mode and automatic end of
interrupt mode.
• The pin diagram and internal block diagram of PIC is shown in figure. The pins are
defined as follows:
CS’(Chip Select signal): To access this chip, chip select signal CS’ is made low. A LOW on
this pin enables RD’ & WR’ communication between the CPU and the 8259A. This signal
is made LOW by decoding the addresses assigned to this chip. Therefore, this pin is
connected to address bus through the decoder logic circuit. Interrupt acknowledge
functions to transfer the control to interrupt service subroutine are independent of CS’.

WR’(Write signal): A low on this pin. When CS’ is low enables the 8259 A to accept
command words from CPU.
RD’(Read signal): A low on this pin when CS’ is low enables this 8259A to release status
(pending interrupts or in-service interrupts or masked interrupts) on to the data bus for
the CPU. The status includes the contents of IMR (interrupt mask register) or ISR (interrupt
service register) or IRR (interrupt request register) or a priority level.
D7-D0 (Data Bus): Bidirectional data bus. Control, status and interrupt vector information
is transferred via this data bus. This bus is connected to BDB of 8085A.
CAS2-CAS0 (Cascade lines): The CAS2-0 lines form a local 8259A bus to control multiple
8259As in master-slave configuration, i.e., to identify a particular slave 8259A to be
accessed for transfer of vector information. These pins are automatically set as output pins
for master 8259A and input pins for a slave 8259A once the chips are programmed as
master or slave.
SP’/ EN’(Salve Program/Enable Buffer): This is a dual function pin. When the chip is
programmed in buffered mode, the pin can be used as an output and when not in the
buffered mode it is used as an input. In non-buffered mode it is used as an input pin to
determine whether the 8259A is to be used as a master (SP’/ EN’= 1) or as a slave (SP’/ EN’
= 0). In buffered mode, normally data bus buffers are used. These buffers need to be
enabled or disabled during transfer of vector information depending upon whether 80259A
is connected before the buffer or after the buffer. To disable/enable the data bus
transceivers (buffers) when data are being transferred from the 8259A to the CPU, this pin
is made low or high.
INT (Interrupt output): This pin goes high whenever a valid interrupt request is asserted. It
is used to interrupt the CPU, thus it is connected to the CPU’s interrupt pin (INTR). In case
of master-slave configuration, the interrupt pin of slave 8259A is connected to interrupt
request input of master 8259A.
INTA’(Interrupt Acknowledge): This pin is used to enable 8259A interrupt vector data on
the data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
IR0-IR7 (Interrupt Request inputs): These are asynchronous interrupt request input pins.
An interrupt request is executed by raising an IR input (low to high), and holding it high
until it is acknowledged. (Edge triggered mode) or just by a high level on an interrupt
request input (Level triggered mode).
A0 (A0 address line): This pin acts in conjunction with the RD’, WR’ & CS’ pins. It is used
by the 8259A to send various command words from the CPU and to read the status. It is
normally connected to the CPU A0 address line. Two addresses are assigned/ reserved in
the I/O address space for each 8259A in the system- one with A0 =0 is called even
address and other with A0 = 1 is called odd address.
Functional Description:
• The 8259A (PIC) has eight interrupt request inputs – IR7 - IR0.
• The 8259A uses its INT output to interrupt the 8085A via INTR pin.
• The 8259A receives interrupt acknowledge pulses from the 𝜇𝑝 at its INTA’ input.
• Vector address, used by the 8085A to transfer control to the service subroutine of the
interrupting device, is provided by the 8259A on the data bus.
• The 8259A is a programmable device that must be initialized by command words sent
by the microprocessor.
• After initialization the 8259A mode of operation can be changed by operation
command words from the microprocessor.
The descriptions of various blocks are given below:
Data bus buffer:
This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to the system data bus. Control words
and status information from the microprocessor to PIC and from PIC to microprocessor respectively, are
transferred through the data bus buffer.

Read/Write & Control Logic: The function of this block is to accept output commands sent from the CPU. It
contains the initialization command word (ICW) registers and operation command word (OCW) registers
which store the various control formats for device operation. This function block also allows the status of
8259A to be transferred to the data bus.
Interrupt Request Register (IRR): Interrupt request register (IRR) stores all the interrupt inputs that are
requesting service. It is an 8-bit register – one bit for each interrupt request. Basically, it keeps track of
which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal
on it, then the corresponding bit in the IRR will be set. The content of this register can be read to know the
status of pending interrupts.
Interrupt Mask Register (IMR): The IMR is used to disable (Mask) or enable (Unmask) individual interrupt
request inputs. This is also an 8-bit register. Each bit in this register corresponds to the interrupt input with
the same number. The IMR operates on the IRR. Masking of higher priority input will not affect the
interrupt request lines of lower priority. To unmask any interrupt the corresponding bit is set ‘0’.
In-service Register (ISR): The in-service register keeps track of which interrupt inputs are currently being
serviced. For each input that is currently being serviced the corresponding bit of in-service register (ISR)
will be set. In 8259A, during the service of an interrupt request, if another higher priority interrupt
becomes active, it will be acknowledged and the control will be transferred from lower priority interrupt
service subroutine (ISS) to higher priority ISS. Thus, more than one bit of ISR will be set indicating the
number of interrupts being serviced. Each of these 3-registers can be read as status register.
Priority Resolver: This logic block determines the priorities of the interrupts set in the IRR. It takes the
information from IRR, IMR and ISR to determine whether the new interrupt request is having highest
priority or not. If the new interrupt request is having the highest priority, it is selected and processed. The
corresponding bit of ISR will be set during interrupt acknowledge machine cycle.
Cascade Buffer/Comparator: This function block stores and compares the IDs of all 8259A’s in the system.
The associated 3-I/O lines (CAS2-CAS0) are outputs when 8259A is used as a master and are inputs when
8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the
CAS2-0 lines. The slave 8259As compare this ID with their own programmed ID. Thus selected 8259A will
send its pre-programmed subroutine address on to the data bus during the next one or two successive
INTA’ pulses.