MICROPROCESSOR AND

ASSEMBLY LANGUAGE
LECTURE-2-COMPUTER ARCHITECTURE

MUHAMMAD HAFEEZ
DEPARTMENT OF COMPUTER SCIENCE
GC UNIVERSITY LAHORE
TODAY’S AGENDA
 Von Neumann Architecture

 Harvard Architecture
VON NEUMANN
ARCHITECTURE

 Up untill Second World War (1939-1944)

computers were used to combat enemy
strategy
 But for a new problem to solve, or carry out
a different task the computer has to be re-
wired/ almost re-built entirely

 What was the solution?

VON NEUMANN
ARCHITECTURE

 In 1945, a mathematician John Von

Neumann proposed the idea of Flexible
Computer – Stored Program Computer

 In the meantime another mathematician

proposed similar type of idea – Turing
Machine

 Both of these computers were

programmable by storing data/ instruction
in the computer memory
VON NEUMANN
ARCHITECTURE

 Advantages:

 Both programs and data were treated equally

 Easier to re-program by loading/ unloading tasks

 Stored-Program Computer is called Von

Neumann Architecture
VON NEUMANN
ARCHITECTURE
FEATURES OF VON
NEUMANN ARCHITECTURE

 Memory:
 The computer will have memory that can hold
data and instructions to process that data.
Today’s RAM
 Control Unit:
 Control unit will manage the processing of data
by coordinating between different components of
Computer – one at a time
 Arithmetic and Logic Unit
 Bus
 Input/ Output Devices
POPULARITY OF VON
NEUMANN ARCHITECTURE
 Most Successful architecture
 Modern Computers have CU and ALU on its
Chip
 Memory concept is manifested as RAM
BOTTLENECKS OF VON
NEUMANN ARCHITECTURE
 Every piece of data has to pass the Data
Bus to reach to CPU and Main Memory
(called von Neumann bottleneck)
 CPU spends most of the time waiting for
instructions
 Solutions?
 Data and Program share the same memory
(Memory Management)
 The rate at which data and instruction are
required often different but in von
Neumann architecture they both reach at
same speed
HARVARD ARCHITECTURE
 Split Program and Data Memory

 Advantages
 Disadvantages
 Application
MACHINE INSTRUCTION
CYCLE
MACHINE INSTRUCTION
CYCLE
 Fetch: The address of instruction moves
from PC to AR. The control unit fetches the
next instruction from the memory at
location pointed by AR into IR, and
increments the Program Counter.
 Decode: The control unit decodes the
instruction to determine what the
instruction will do. The instructions input
operands are passed to the ALU, and
signals are sent to the ALU indicating the
operation to be performed
MACHINE INSTRUCTION
CYCLE
 Fetch operands: If the instruction uses an
input operand located in memory, the
control unit uses a read operation to
retrieve the operands and copy it into data
registers (DR)
 Execute: The ALU executes the instruction
using the Accumulator register and data
register as operands and sends the output
to Accumulator register and/or memory.
The ALU updates status flags providing
information about the processor state.
 Store output operand: If the output
operand is in memory, the control unit uses
a write operation to store the data
CPU PERFORMANCE
DEPENDS UPON MEMORY
READ/ WRITE
READING FROM MEMORY
 Cycle 1: The address bits of memory
operands are placed on Address Bus
(ADDR)
 Cycle 2: The Read Line (RD) is set low,
indicating memory that a read operation is
to be performed
 Cycle 3: CPU waits for Memory to respond,
during this cycle memory controller places
the operand on data bus (DATA)
 The Read Line (RD) set high indicating the
CPU to read data from data bus.
MEMORY DELAYS

 How to solve this speed mismatch?

SIZE OF MEMORY
 A Kilobyte = 1024 Bytes
 A Megabyte = 1024 Killobytes = 220 or
(1,048,576 Bytes) 1 million
 A Gigabyte = 230 or 1 billion bytes
 A Terabyte = 240 or 1 trillion bytes

 Example:
 A computer has 16MB Memory, How many
bytes?
DATA BUS AND ADDRESS
BUS
 Data Bus: Bi-Directional Bus to carry data
in/out of RAM, more wider the bus more
data can travelled .. Cost increase too

 Address Bus: Uni-Directional Address lines

of Address Bus determine number of
locations of memory to be addressed e.g. x
lines can address 2x memory location, each
location usually hold 1 byte of contents,
memory called byte addressable memory
 Number of address lines required to
address 1K memory?
REGISTERS OF CPU
 A location within CPU to hold temporary
data and instructions
 General Purpose Registers
 Special Purpose Registers

 But we will discuss registers in more generic

way, a specialized register with respect to
specific architecture will be discussed later
REGISTERS OF CPU
 More General Type of Registers
 Program Counter
 Instruction Register
 Address Register
 Data Registers
 Accumulator
 Program Status Word or Flag Register
 I/O Registers

 Note: No Registers with these name exist in

today’s computers
QUESTIONS

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