Microprocessor system

Microprocessor system
Elements of a Microprocessor system

CPU
• Central processing unit. This performs the
Registers RAM | ROM
arithmetic and logical operations, such as
program data
add/subtract, multiply/divide, binary storage storage
manipulation, and so on.

• Memory. This holds both the program Control, data, address bus

instructions and program/system data. ALU

Control
unit input
output
unit unit
 Microprocessor system
Elements of a Microprocessor system

CPU
• Input device. This is used to read data into
Registers RAM | ROM
the memory. Example input devices are
program data
keyboards, disk storage, etc). The input storage storage
device loads both program instructions and
data into memory.
Control, data, address bus

• Output device. This is used to output data ALU

from memory to an output device, such as

a printer, display device, etc. Control
unit input
output
device device
 Microprocessor system
Elements of a Microprocessor system
CPU

Registers RAM | ROM

program data
storage storage

System buses: Control, data, address

ALU

Control
unit
output input
unit unit

System buses : ( Transfers data between components inside the computer or between computers )
Address bus (carry address)
Data bus (carry data)
Control bus (control & coordination)
 Microprocessor system
Elements of a Microprocessor system
CPU

Registers

Address Bus
RAM | ROM

program data
storage storage

 Address = binary number that

identifies a specific memory storage
location or I/O port involved in a
Control, data, address bus
data transfer ALU

 Address Bus = pathway transmit

Control
address to memory or I/O port. unit input
output
unit unit

 Address Bus is unidirectional (one

way): addresses are always issued by
the MPU
 Microprocessor system
Elements of a Microprocessor system

Data Bus
CPU

Registers RAM | ROM

program data
 The Data Bus carries the data which is storage storage

transferred throughout the system.

( bi-directional)
Control, data, address bus

 Examples of data transfers ALU

 Program instructions being read

from memory into MPU. Control

 Data being sent from MPU to I/O unit

output input

port unit unit

 Data being read from I/O port

going to MPU
 Results from MPU sent to Memory

 These are called read and write

operations
 Microprocessor system
Elements of a Microprocessor system

Control Bus
CPU

Registers RAM | ROM

program data

 Control Bus = group of control signals storage storage

 Control signals are unidirectional, and are

mainly outputs from the MPU.
Control, data, address bus
 provide synchronization (timing control) ALU
between MPU and other components.

Control
 Example unit
output input
 RD: (read signal) read data into MPU unit unit
 WR: (write signal) write data from MPU
 Classification of Microprocessor Systems
• Small embedded systems
– small processing elements, which have minimal input and output,
and have a simple program which runs on the processor.
– have their own local permanent memory
– do not require an operating system, and the code runs directly
on the processing element.

• Large embedded systems

– have a powerful processor, which can have many inputs and
outputs, and perform complex operations
– typically programmed once for their operation, and then not
programmed again, until an upgrade is required
– if they only run one program, they do not require an operating
system, but if many processes are run at a time, there is
normally a a basic operating system which supports the running
of several programs at a time
 Classification of Microprocessor Systems (cont.)
• Mobile systems
– have medium-power processors, and have limited memory
resources
– have a remote connection to another device, such as over
an infrared link or a radio link (as with a mobile phone)
– many of their programs are embedded into the system
– with an embedded operating system.

• Desktop systems
– general-purpose computers, which can be installed with any type
of operating system, and any user program which can be supported
on the installed operating system
– can have a large range of hardware and software installed on them
 Classification of Microprocessor Systems (cont.)
• Server systems
– have a definite purpose of running server programs for client computers.
– robust, and have large amounts of memory to run many consecutive
connections
– may also have several different storage sources, which allow for one or more
to fail, without a loss of data
– not as reliable as embedded systems, as they support a wide range of
hardware and software, but these tend to be more robust than the types used
in a desktop system

• Supercomputers
– extremely fast computers, with an optimized architecture.
– have multiple processors, with a fast communications channel between them
– have a base performance speed which is at least 10 times as great as a top-of-
the-range desktop computer
 Classification of Microprocessor Systems (cont.)

• Control systems
– support the interfacing of many devices, with some form of
control program
– as this control must be achieved within given time limits, there
must be a robust and powerful operating system to support fast
response speeds
– must be able to prioritize signals, as the safety critical control
should have a higher priority over optimization controls
Internal Architecture of a Generic Microprocessor
 Internal Architecture of a Generic Microprocessor

External Address Bus

• Arithmetic logic unit (ALU)

Memory Addr Reg

• Accumulator General
Registers

• Clock signals
Program Counter

• Control unit Stack Pointer

• Internal data bus Internal Data Bus

• Program counter (PC) Instruction

External Data Bus

Register
Accumulator Temp Reg

• General purpose registers Instruction

Decoder
C
• Instruction register (IR) Status
Z

registers N
ALU
• Memory address register (MAR) RESET

Control Unit
Clock
• Status registers (SR)

IOR# IOW# MEMR# MEMW# INTR INTA# MPU

Internal Architecture

External Address Bus

Memory Addr Reg

General
Arithmetic logic unit (ALU): Registers

perform logical (AND, OR, NOT, Program Counter

XOR, ...) (Boolean) and Stack Pointer

mathematical operations (+, ,

x, / ... ), and store the results in the Internal Data Bus

accumulator Instruction

External Data Bus

Register
Accumulator Temp Reg

Accumulator: store all immediate Instruction

results from ALU

Decoder
C
Status Z
registers
N

Clock signals: synchronize and RESET

ALU

coordinate operations Clock

Control Unit

IOR# IOW# MEMR# MEMW# INTR INTA# MPU

Internal Architecture

Control unit: carry out instructions External Address Bus

Internal data bus: transfer data

between the components within the
Memory Addr Reg

General
computer Registers

Program counter (PC): Program Counter

A pointer to the current location

Stack Pointer

of the program
Internal Data Bus
Keeps track of the memory
location
Instruction

External Data Bus

Register
Accumulator Temp Reg

Once an instruction is fetched, Instruction

it will increment by 1 to move to

Decoder
C
Status Z

next instruction registers

N
ALU

Should not be modified, or

RESET

Control Unit
serious error can result Clock

Need to use special instructions

(e.g. JUMP) to modify IOR# IOW# MEMR# MEMW# INTR INTA# MPU
Internal Architecture

External Address Bus

General purpose registers:
temporary storage of binary Memory Addr Reg

numbers, or additional data during General

the execution of a program Registers

Instruction register (IR): temporary

storage of the current instruction of a Program Counter

Stack Pointer

program
Memory address register (MAR): Internal Data Bus
Holds the address of the next
instruction Instruction

External Data Bus

Register

Feeds the address bus with the

Accumulator Temp Reg

addresses of the current Instruction

Decoder

program Status
C
Z

Status register (SR): registers

N
ALU
Contains flags which indicate RESET

certain conditions Clock

Control Unit

SR must be either 0 or 1
IOR# IOW# MEMR# MEMW# INTR INTA# MPU
How the CPU Executes Program Instructions
Before execute an instruction, program instructions and data must be
placed into memory from input device or secondary memory

The CPU performs four steps in executing an instruction

1. The control unit gets the instruction from memory.
2. The control unit decides what the instruction means and
directs the necessary data to be moved from memory to
the arithmetic/logic unit.
3. The arithmetic/logic unit performs the actual operation on
the data.
4. The result of the operation is stored in memory or a register.

The first two steps make up what is called the instruction time, or fetch cycle
The last two steps make up what is called the execution time, or execution cycle.
The combination of the fetch cycle and execution cycle is called a machine cycle
Each type of central processing unit is designed to understand a specific group of
instructions called the instruction set
 Instruction Fetch

Obtain instruction from input

1. PC is enabled to address bus

2. The addressed memory is enabled to data
bus
3. The data bus is enabled to the decoded
instruction
4. PC is incremented by 1 (+1) to move to the
next instruction
Repeat instruction fetch if the
instruction is “no operation” (NOP)
Otherwise, execute the instruction
Instruction Execution
8086 Signals
 8086/8 Internal Organization

Address Bus Data Bus

Processor Model

Addr generation
Bus Controller
BIU

AH AL
BH BL ADD

CH CL 1
DH DL
EU BP
2
Instruction
3
CS Queue
DI 4
ES
SI 5
SS
SP 6
DS
IP

Internal Data Bus

ALU

FLAGS
 Registers

Address Bus Data Bus

• Registers are storage locations

BIU

• The first-level of a computer’s

Addr
generation
Bus Controller

memory hierarchy A
H
A
L
ADD
B B

• The fastest to access storage in

H L
C C 1
H L
EU D D 2
H L

your system B
P
D
I
C
S
E
3

4
Instruction
Queue

S S 5

• Purposes
I S
S S
6
P D
S
I

– Data used in arithmetic/logical

P

operations
Internal Data Bus

– Pointers to memory locations containing ALU

data or instructions FLAG

S

– Control information (e.g. outcome of

arithmetic instructions, outcome of
instructions that change the control flow
of a program)
x86 Registers at a Glance

Special Registers

Instr Pointer IP
EIP
Flags FLAG
EFLAG
 General Purpose Registers

General Purpose
• Accumulator (AH,AL,AX,EAX)
– Accumulates results from mathematical calculations AH AL
Accumulator
• Base (BH,BL,BX,EBX) AX
EAX
– Points to memory locations
BH BL
• Count (CL,CH,CX,ECX) Base
BX
– Counter used typically for loops EBX

– Can be automatically incremented/decremented Count

CH CL
CX
• Data (DL,DH,DX,EDX) ECX
– Data used in calculations DH DL
Data
– Most significant bits of a 32-bit mul/div operation DX
EDX
 Index Registers

• SP, ESP
– Stack pointer Index Registers
• BP, EBP
– Address stack memory, used to access Stack Pointer SP
subroutine arguments ESP

• Base Pointer BP
SI, ESI, DI, EDI
EBP
– Source/Destination registers
Dest Index DI
– Point to the starting address of a
EDI
string/array
Source Index SI
– Used to manipulate strings and similar
ESI
data types
 Segment Registers

• CS
– Points to the memory area where your
program’s instructions are stored
Segment Registers
• DS
– Points to the memory area where your CS Code Segment
program’s data is stored
DS Data Segment
• SS ES Extra Segment
– Points to the memory area where your
SS Stack Segment
stack is stored
FS
• ES,FS,GS
GS
– They can be used to point to
additional data segments, if
necessary
 Special Registers

• IP, EIP
– Instruction pointer, points
Special Registers
always to the next instruction
that the processor is going to Instr Pointer IP
execute EIP
• FLAG, EFLAG Flags FLAG
– Flags register, contains
EFLAG
individual bits set by different
operations (e.g. carry, overflow,
zero)
– Used massively with branch
instructions
 The Flags

• RFLAGS indicate the condition of the microprocessor and control its operation.
• The Figure shows the flag registers of all versions of the microprocessor.
• Flags are upward-compatible from the 8086/8088 through Core2 .
• The rightmost five and the overflow flag are changed by most arithmetic and logic
operations.
– although data transfers do not affect them
• Flags never change for any data transfer or program control operation.
• Some of the flags are also used to control features found in the microprocessor.
 The Flags

• C – holds a carry or a borrow

• P – the parity flag (little use today)
• A – auxiliary flag used with DAA and DAS
• Z – zero
• S – sign
• O – Overflow
• D – direction (used with string instructions)
• I – interrupt (interrupt on/off)
• T – trace flag (trace on/off)
 Newer Flag Bits

• IOPL – I/O privilege level for

Windows
• NT – nested task
• RF – resume flag
• VM – virtual mode
• AC – alignment check
• VIF – virtual interrupt
• VIP – virtual interrupt pending
• ID = CPUID instruction available
 List of Each Flag bit, with a brief description of function.

• C (carry) holds the carry after addition or borrow after subtraction.

– also indicates error conditions
• P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic
1 for even parity.
– if a number contains three binary one bits, it has odd parity; If a number contains no one bits,
it
has even parity
• A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction
between bit positions 3 and 4 of the result.
• Z (zero) shows that the result of an arithmetic or logic operation is zero.
• S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction executes.
• T (trap) The trap flag enables trapping through an on-chip debugging feature.
• I (interrupt) controls operation of the INTR (interrupt request) input pin.
• D (direction) selects increment or decrement mode for the DI and/or SI registers.
• O (overflow) occurs when signed numbers are added or subtracted.
– an overflow indicates the result has exceeded
the capacity of the machine
 List of Each Flag bit, with a brief description of function.

• IOPL used in protected mode operation

to select the privilege level for I/O devices.
• NT (nested task) flag indicates the current task is nested within another task in
protected mode operation.
• RF (resume) used with debugging to control resumption of execution after the next
instruction.
• VM (virtual mode) flag bit selects virtual mode operation in a protected mode system.
• AC, (alignment check) flag bit activates if a word or doubleword is addressed on a non-
word or non-doubleword boundary.
• VIF is a copy of the interrupt flag bit available to the Pentium 4–(virtual interrupt)
• VIP (virtual) provides information about a virtual mode interrupt for (interrupt pending)
Pentium.
– used in multitasking environments to provide virtual interrupt flags
• ID (identification) flag indicates that the Pentium microprocessors support the
CPUID instruction.
– CPUID instruction provides the system with information about the Pentium
microprocessor
 Segment Registers
• Segment registers define the start of a section (segment) of
memory for a program.
• A segment is either:
- 64K (216) bytes of fixed length (real mode), or
- Up to 4G (232) bytes of variable length (protected mode).
• Generate memory addresses when combined with other
registers in the microprocessor.
• A segment register functions differently in real mode than in
protected mode.
• Following is a list of each segment register, along with its
function in the system.
• CS (code) segment holds code (programs and procedures) used by the
microprocessor.
• DS (data) contains most data used by a program.
– Data are accessed by an offset address or contents of other registers that
hold the offset address
• ES (extra) an additional data segment used by some instructions to hold
destination data.
• SS (stack) defines the area of memory used for the stack.
– stack entry point is determined by the stack segment and stack pointer
registers
– the BP register also addresses data within
the stack segment
• FS and GS segments are supplemental segment registers available in 80386–
Core2 microprocessors.
– allow two additional memory segments for
access by programs
• Windows uses these segments for internal operations, but no definition of their
usage
is available.
 Real Mode Memory Addressing
• Used by the DOS operating system
• The only mode available on the 8086-8088:
20 bit address bus  1 MB, 16 bit data bus, 16 bit registers
• 80286 and above operate in either the real or protected mode.
• Real mode operation allows addressing of only the first 1M
byte of memory.
– the first 1M byte of memory is called the real memory, conventional
memory, or DOS memory system
 Real Mode Memory Addressing
• Real mode 20-bit addresses are obtained by
combining a segment number (in a segment
Logical Address: segment offset

register) and an offset address (in

another processor register)
• The segment register address (16-bits) is x16 +

appended with a 0H or 00002 (or multiplied by

10H or 16d) to form a 20-bit start of segment
Physical Address:
Operand’s effective address
address
• Then the effective memory address (EA) =

this 20-bit segment start address + the 16-bit

offset address in another processor register
• For the 8086, segment length is fixed @ 2 16 =
64K bytes (determined by the size of the
offset registers)
 Real-Mode Address-Translation

16-bit segment-address 16-bit offset-address

Logical address: 0x1234 0x6789

0x12340
+ 0x06789 x 16 +
----------------
0x18AC9
20-bit bus-address
Physical address: 0x18AC9
 (11MB)
MB

EA (Effective Address) of byte accessed

20-bit (5-byte) 64 KB +
Physical Segment 16-bit each
Memory address

Appended 4 bits (0H)

Segment number
In Segment Register
 Effective Address Calculations

• EA = segment register (SR) x 10H + offset

(a) SR: 1000H
10000 + 0023 = 10023
(b) SR: AAF0H
AAF00 + 0134 = AB034
(c) SR: 1200H
12000 + FFF0 = 21FF0
 Defaults
Convention Example: EA = CS:[IP]
• Default segment numbers in:
– CS for program (code) Segment number Offset: Literal
– SS for stack in Segment register, or in a CPU register
defines the start of the locates the next
– DS for data code segment instruction within the
– ES for string (destination) data code segment.
• Default offset addresses that go with them:

Segment Offset (16-bit) Offset (32-bit) Purpose

8080, 8086, 80286 80386 and above
IP (locates the next instruction within the EIP Program
CS code segment)

SP, BP (address memory location at ESP, EBP Stack

SS the stack segment)

BX, DI, SI, 8-bit or 16-bit # EBX, EDI, ESI, EAX ECX, Data
DS EDX, 8-bit or 32-bit #
DI, with string instructions EDI, with string instructions String
ES destination
 Stack

• Call, Return, Push and Pop instructions

• In the real mode, the stack is 64 K long
 Segmentation: Pros and Cons
Advantages:
• Allows easy and efficient relocation of code and data
• To relocate code or data, only the number in the relevant
segment register needs to be changed
Consequences:
A program can be located anywhere in memory without making
any changes to it (addresses are not absolute, but offsets
relative to start of segments)
Program writer needs not worry about actual memory structure
(map) of the computer used to execute it

Disadvantages:
• Complex hardware and for address generation
• Address computation delay for every memory access
• Software limitation: Program size limited by segment size
(64KB with the 8086)
 Limitations of the above real mode segmentation scheme

• Segment size is fixed at and limited to 64 KB

• Segment can not begin at an arbitrary memory address…
With 20-bit memory addressing, can only begin at addresses starting with 0H, i.e. at
16 byte intervals
 Principle is difficult to apply with 80286 and above, with segment registers
remaining at 16-bits!
Append: 00H 0000H

80286 and above use 24, 32 bit addresses but still 16-bit segment registers
• No protection mechanisms: Programs can overwrite operating system code
segments and corrupt them!

 Use memory segmentation in the protected mode