Timing Analysis of

Cyclic Combinational Circuits

Marc D. Riedel and Jehoshua Bruck
California Institute of Technology
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Marrella splendens Cyclic circuit

IWLS, Temecula Creek, CA, June 4, 2004

 Combinational Circuits
The current outputs depend only on the current inputs.

inputs outputs

x1 a f1 ( x1 ,  , xm )
x2 a f 2 ( x1 ,  , xm )
combinational
 logic 
a f n ( x1 ,  , xm )
xm

xi  {0,1} f j : {0,1}m  {0,1}

i  1,  , m j  1,  , n
 Combinational Circuits
Generally acyclic (i.e., feed-forward) structures.

c
y AND
z OR

x AND

z
y XOR
s
XOR
 Cyclic Combinational Circuits
Circuit is cyclic yet combinational;
computes functions f1 and f2 with 6 gates.
x AND

a OR

( x  f1 )))
f1  b( a  x (d  c ))
b AND

An acyclic circuit computing these

x OR functions requires 8 gates.

c AND

f2  d  c ( x  b (aa)  x f2 ))
d OR
 Timing Analysis
Predicated on a topological ordering.

x l1 = 1 l4 = 3
c
y g1 l3 = 2
z g4

x l2 = 1
g3
z l5 = 2
y g2 s
g5
level: li  max l j + 1
j  fanin( g i )
 Timing Analysis
Predicated on a topological ordering.

1x0 l1 = 1 l4 = 3
11
c12
1y0 g1 1z0 l3 = 2
g4

l2 = 1 02
1x0 g3
1z0 l5 = 2
01
arrival times 1y0 g2 s12
g5
level: li (assume j + 1 bound of 1 time unit for each gate)
max aldelay
j  fanin( g i )
 Cyclic Combinational Circuits
No topological ordering.
x AND How can we perform timing analysis?

a OR

f1  b( a  x (d  c ))
b AND

x OR

c AND

f2  d  c ( x  b a )
d OR
 Cyclic Combinational Circuits
14 No topological ordering.
1x0 AND How can we perform timing analysis?
15
a00 OR

1f16  b( a  x (d  c ))
1b0 AND

1x0 11
OR

12
1c0 AND

1f23  d  c ( x  b a )
d00 OR
 Prior Work

In previous papers, we presented:

• Algorithms for functional analysis (IWLS’03);

• Strategies for synthesis (DAC’03).

In trials on benchmark circuits, cyclic optimizations reduced

the area of by as much as 30%
Optimization for Area
application of “script.rugged” and mapping

Benchmark Berkeley SIS Caltech CYCLIFY Improvement

5xp1 203 182 10.34%
ex6 194 152 21.65%
planet 943 889 5.73%
s386 231 222 3.90%
bw 302 255 15.56%
cse 344 329 4.36%
pma 409 393 3.91%
s510 514 483 6.03%
duke2 847 673 20.54%
styr 858 758 11.66%
s1488 1084 1003 7.47%

Number of NAND2/NOR2 gates in

Berkeley SIS vs. CYCLIFYsolutions
 Contributions

In this paper, we discuss:

• An algorithm for timing analysis.

• Synthesis results, with optimization jointly targeting
area and delay.

In trials on benchmarks circuits, cyclic optimizations

simultaneously reduced the area by up to 10% and the
delay by up to 25%.
 Related Work
Malik (1994), Hsu, Sun and Du (1998), and Edwards (2003)
considered analysis techniques for cyclic circuits.

Their approach: identify equivalent acyclic circuits.

inputs    outputs
acyclic
cyclic
circuit
 

minimum-cut
feedback set
Unravelling cyclic circuits this way is a difficult task.
 Our Approach
Perform event propagation, directly on a cyclic circuit.

10
00
cyclic 16
inputs 10 outputs
circuit 13
10
00
 Our Approach
Perform event propagation, directly on a cyclic circuit.
Compute events symbolically, with BDDs.

[x]0
[a]0
cyclic f1=[b(a+x(c+d))]6
[b]0
circuit f2=[d+c(x+ba))]6
[c]0
[d]0
 Circuit Model
Perform static analysis in the “floating-mode”. At the outset:
• all wires are assumed to have unknown/undefined values ( ).
• the primary inputs assume definite values in {0, 1}.

0
0

AND 1
a “controlling” input 1
1
AND 1
full set of 

“non-controlling” inputs AND
unknown/undefined
output
 Circuit Model
Perform static analysis in the “floating-mode”. At the outset:
• all wires are assumed to have unknown/undefined values ( ).
• the primary inputs assume definite values in {0, 1}.

 


1 AND
 OR

During the analysis, only signals driven (directly or indirectly) by

the primary inputs are assigned definite values.
 Circuit Model
Up-bounded inertial delay model.
Ensures monotone speed-up property.

AND

each gate has delay in [0, td]

 Circuit Model
The arrival time at a gate output is determined:
• either by the earliest controlling input.

02

13 03

06 AND

(assuming a delay bound of 1)

 Circuit Model
The arrival time at a gate output is determined:
• either by the earliest controlling input;
• or by the latest non-controlling input.

12

13 17

16 AND

(assuming a delay bound of 1)

 Timing Analysis

Characterize arrival times symbolically (with BDDs):

C ( 0) : set of input assignments that produce 0

 (1)
C : set of input assignments that produce 1

Implicitly:

C ( 0)  C (1) : set of input assignments for which output is 

 Timing Analysis

Characterize arrival times symbolically (with BDDs):

C ( 0) : set of input assignments that produce 0

 (1)
C : set of input assignments that produce 1

Time-stamp the characteristic sets:

C ( v ) t
arrival time
 Initialization

internal signals:

[C ( 0 ) ]0  0
 (1)
[C ]0  0

primary inputs:
[C ( 0 ) ]0  x
x  (1)
[C ]0  x
 Propagation

If there is a change in the characteristic set of a gate’s fan-in:

Ci(v )
Cj(w)

For a controlling input value v, producing an output value w,

C (j w) : C (j w)  Ci( v )
 Propagation

If there is a change in the characteristic set of a gate’s fan-in:

Ck(1v1 )
Ck(2v2) Cj(w)
Ck(3v3)

For non-controlling input values v1, v2, v3 producing an output

value w,
C ( w)
j : C ( v1 )
k1 C ( v2 )
k2 C ( v3 )
k3
 Propagation

If there is a change in the characteristic set of a gate’s fan-in:

Cj(w)

delay in [0, td]

If Cj(w) changes as a result, update its time-stamp:

[C (j w) ] t:t td
 Example C1( 0)  0x  d c
 (1)
time 6
1
2
3
4
5 C1  0xxd( d  c )
AND

C2( 0)  0a x( x  d c )
x g1 OR  (1)
C2  0a  xxd(d  c)
a g2 AND C3( 0)  0b  a (xx  d c )
 (1)
C3  0b(aa  x (dd)  c ))
b g3
OR
C4( 0)  0x (ba  b )
 (1)
C4  0x  b a
x g4 AND
C5( 0)  0c  x b(b  a )
 (1)
C5  0c(xx  b a )
c g5 OR

C6( 0)  0d (cc  x b(b)  a ))

 (1)
d g6 C6  0d  ccx( x  b a )
 Timing Analysis
• The algorithm terminates since the cardinality of each set Ci(v )
increases over time; at most Ci  1 .
(v)

• The circuit is combinational iff the “care” set of input assignments

is contained within
Ci( 0 )  Ci(1)
for each output gate gi .

• The delay bounds on the arrival times for the output gates
give a bound on the circuit delay.
Multi-Terminal BDDs f2

1
d
0

11 c
For finer-grained timing information,
preserve a history of the changes.
02 x

f2  d  c ( x  b a )
13 b
Reference: Bahar et al., “Timing Analysis
using ADDs"
04 a

15 06
 Synthesis
N1

Select best solution through a N3 N2

branch-and-bound search.

N4 N6
Analysis algorithm is used to
validate and rank potential
solutions. N5 N7

N9 N8

See The Synthesis of Cyclic Combinational Circuits, DAC’03.

 Implementation: CYCLIFY Program
• Incorporated synthesis methodology in a general logic
synthesis environment (Berkeley SIS package).
• Trials on wide range of circuits
– randomly generated
– benchmarks
– industrial designs.
• Conclusion: nearly all circuits of practical interest can be
optimized with feedback.
Optimization for Area and Delay
application of “script.delay” and mapping
Berkeley SIS Caltech CYCLIFY
benchmark Area Delay Area Improvement Delay Improvement
p82 175 19 167 4.57% 15 21.05%
t1 343 17 327 4.66% 14 17.65%
in3 599 40 593 1.00% 33 17.50%
in2 590 34 558 5.42% 29 14.71%
5xp1 210 23 180 14.29% 22 4.35%
bw 280 28 254 9.29% 20 28.57%
s510 452 28 444 1.77% 24 14.29%
s1 566 36 542 4.24% 31 13.89%
duke2 742 38 716 3.50% 34 10.53%
s1488 1016 43 995 2.07% 34 20.93%
s1494 1090 46 1079 1.01% 39 15.22%

Area and Delay of Berkeley SIS vs. CYCLIFYsolutions.

Area: number of NAND2/NOR2 gates.
Delay: 1 time unit/gate.
 Discussion

Analysis through symbolic event propagation:

• Existing methods can be applied to cyclic circuits.
• Complexity is comparable for cyclic and acyclic circuits.

Synthesis strategies targeting area and delay:

• Nearly all circuits can be optimized with cycles.
• Optimizations are significant.
 Future Directions

• Apply more realistic timing models for analysis.

• Use more efficient symbolic techniques (e.g., use boolean
satisfiability (SAT)-based techniques).
• Incorporate more sophisticated search heuristics into synthesis.