Tutorial 11

Digital Logic Design (ELCT201) – Spring 2020

Eng. Yasmin Massoud
Agenda
• Registers
• Load Register
• Serial Register
• Universal Shift Register

• Counters
• D Flip-Flop counter
• JK up down counter
 1-Load Register
Problem I: Using D flip-flops and 2×1 multiplexers, implement a 4 - bit parallel-input
register
𝑖  0 𝐷 0 𝑜  0
•  Input is
 𝑄 𝑡 +1 = 𝐷

• Output appears on nxt

positive clk edge 𝑖  1 𝑜  1
𝐷  1

clk

𝑖  0 𝑖  2 𝑜  2
𝐷  2
𝑜  0

𝑖  3 𝐷  3 𝑜  3
Problem I: Using D flip-flops and 2×1 multiplexers, implement a 4 - bit parallel-input
register

 • What if we need to choose to load new 𝑖 0 𝑖 0

values 𝑜  0 𝐷 0 𝑜  0
Or keep the old output
 𝑂 𝑡 +1 =𝑂 𝑡 𝑠  𝑖 1
𝑖 1
𝑖 0 𝑜  1 𝐷𝐷 1 1 𝑜  1
𝑜  0 𝐷  0
𝑠 
𝑠  𝑖 2 𝑖 2
 • if S = 0, = 𝑜  2 𝐷𝐷 2 2 𝑜  2
If S= 1, =
t+1 t 𝑠  𝑖 3
 • If s =0 = 𝑖 3
𝑜  3 𝐷 𝐷3  3 𝑜  3
 • If s =1 =
𝑠 
2-Serial Register :
Problem V: The contents of a 4 -bit register are initially 1011. The register is shifted 6
times to the right, with the serial input being 101101. What are the contents of the of
the register after each shift?

1 0 1 1 0 1

101101 1011

1 0 1 1
Serial
Input 𝐷 0 𝑂
  0 𝐷 1 𝑂
  1 𝐷 2 𝑂
  2 𝐷 3 𝑂
  3
Serial Register :
Input
Serial input : -- 1
1 0
0 1
1 1
1
1 0 1 1 0 1 1 1 1 0 1
1 1 1 0 1
0
0 0
0 1
1 1
1 0
0
1
1 1
1 0
0 1
1 1
1
1
1 1
1 1
1 0
0 1
1
0
0 0
0 1
1 1
1 0
0
1
1 1
1 0
0 1
1 1
1

Serial 1 0 1 1
 𝐷0
Input
 𝐷0  𝐷0  𝐷0
𝑂0
 
𝑂 1  𝑂 2
  𝑂3
 
 3-Universal Shift Register
Problem IV: Sketch the logic diagram of a 2 -bit universal shift
register

1) Operation of Universal Shift Register

 • 2 output bits :

Input
  𝑖𝑝
 :serial input for shift right
Operation Output

00 No change    𝑖𝑝 𝑄 1
01 Shift Right    :serial input for shift left
10 Shift Left  
11 𝑖  1 𝑖 0   𝑖𝑝
Parallel Load  
2) Design of Universal Shift Register
Input Operation Output

• No. of FF= no. output bits

00 No change   • No. of Muxes =no.of FF.
01 Shift Right   • Mux is 4x1 (4 operations)
10 Shift Left  
11 Parallel Load  𝑖 1 𝑖 0

𝑖  0 𝐷 0 𝑄
  0
No change
Shift Right
𝑖  0
Shift Left
Parallel Load
𝑖  1 𝑄  1
 𝐷 1
No change
Shift Right  𝑖 1
Shift Left
Parallel Load
2) Design of Universal Shift Register (connections)
Input Operation Output

00 No change  
01 Shift Right  
10 Shift Left  
11 Parallel Load 𝑖  1 𝑖 0

𝐷
  1  
Ip
𝑄  1 𝐷 0   𝑄  ip0

𝑆  11
00𝑆
01
10
1 0 𝑆  11
00𝑆
01
10
1 0

𝑄1 𝑖 𝑝 𝑄0 𝑖1 𝑄
𝑄00
𝑄
𝑄 𝑖𝑄
   00𝑄𝑄
1𝑝
𝑖111
𝑄 ¿0𝑖 𝑖¿
    ¿
𝑖𝑝
¿
𝑖𝑝 0 1
Solve This !
• Implement a 3 bit-universal Shift Register
Counters
Problem III: Design a 3 -bit synchronous up counter that starts at state 000 and only goes through
the states with an even decimal equivalent. The safest-possible circuit should be implemented in
your design. Assume that the counter is cyclic (i.e. upon reaching the last possible state, it would go
back to 000).
 𝑄 𝑡 +1  𝐷
1. Define inputs, outputs, possible states
• S0 :000
• S2 :010 3.State Table
• S4: 100 Prsnt Nxt FF.inp
• S6: 110
ABC ABC
S0 000 010 010
2. State Diagram: 𝑄
  𝑡 +1 =𝐷
001 000 000
S2 010 100 100
S0 000
011 000
S4 100 110 110
S6 S2
101 000 000
S4 S6 110 000 000
111 000 000
Problem III: Design a 3 -bit synchronous up counter that starts at state 000 and only goes through
the states with an even decimal equivalent. The safest-possible circuit should be implemented in
your design. Assume that the counter is cyclic (i.e. upon reaching the last possible state, it would go
back to 000).

4. Draw Circuit

Presen Next BC 00 01 11 10
t A mo m1 m3 m2
0 1 𝐷
  𝐴 =𝐶 ′ ( 𝐴 𝑥𝑜𝑟𝐵)
ABC ABC m4 m5 m7 m6
1 1
000 010 010
001 000 0 BC
001 000 0000
0 00 01 11 10

010 100 100 A0 mo m1 m3 m2

1 ′
010 100 100 m4 m5 m7 m6  𝐷 𝐵 =𝐶 𝐵 ′ ¿
011 000 000 1 1
011 000 000
100 110 110
100
101 110
000 1
0100
0 BC 00 01 11 10
mo m1 m3 m2
101
110 000
000 0
0000
0 A0
  𝐷 𝑐 =0
110
111 000 000 1
m4 m5 m7 m6

111 000 000

4. Draw Circuit(cont.)
C’
A 𝑄  𝐴
𝐷 𝐴
B
𝐷
  𝐴 =𝐶 ′ ( 𝐴 𝑥𝑜𝑟𝐵)

C’ 𝐷 𝐵 𝑄  𝐵
′
 𝐷 𝐵 =𝐶 𝐵 ′ ¿ B’

0 𝐷 𝐶 𝑄  𝐶
  𝐷 𝑐 =0
Problem II: Consider the following synchronous 4 - bit binary counter. How can the addition of 2×1
multiplexers to the circuit allow it to be used as a count up/down counter? Sketch a new logic
diagram
for such a circuit.

0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0
0 0
1 1
0 1
0
0
0 1
1 0
0 0
1
0 1 0
1 1
0
𝐴
  3 𝐴2 𝐴 1 𝐴 0 0 1 1 1
0
1
0 0
1 0
1 0
1
 • Let Count Enable(E ) = 1 1
1
0
0
0
0
1
0
• FF0: ,always toggle 1
1
0
0
1
0
0
1
• FF1:.E 1
1
0
0
1
1
1
0
1 1 0 0
• FF2: = . . 1
1
0
1
1
0
1
1
• FF3: = . = . 1
1 1
1 0
1 0
0
1
1 1
1 0
1 1
1
1 1 1 0
1 1 1 1
0 0 0 0 11 1
0 0 0 1
11 0
0 0 1 0
11 1
0 0 1 1 11 0
0 1 0 0 11 1
0 1 0 1 11 0
0 1 1 0
11 1
0 1 1 1
11 0
1 0 0 0 11 1
1 0 0 1 11 0
1 0 1 0 11 1
1 0 1 1
11 0
• 
•
Let Count Enable(E ) = 1
FF0: ,always toggle
1 1 0 0
11 1
1 1 0 1 11 0
1 1 1 0 11 1
1 1 1 1 11 0
  

0 0 0 0 00 11 0 1
0 0 0 1 11 11 1 0
0 0 1 0 00 11 1 1
0 0 1 1 11 11 0
0
0 1 0 0 00 11 0 1
0 1 0 1 11 11 1 0
0 1 1 0 00 11 1 1
0 1 1 1 11 11 0 0
1 0 0 0 00 11 0 1
1 0 0 1 11 11 1 0
1 0 1 0 00 11 1 1
1 0 1 1 11 11 0 0 •  Let Count Enable(E ) = 1
1 1 0 0 00 11 0 1 • FF0: ,always toggle
1 1 0 1 •
11 11 1 0
FF1:.E

1 1 1 0 00 11 1 1
1 1 1 1 11 11 0 0
  

0 0 0 0 00 00 11 0 0 1
0 0 0 1 00 11 11 0 1 0
0 0 1 0 00 00 11 0 1 1
0 0 1 1 11 11 11 0
1 0
0 1 0 0 00 00 11 1 0 1
0 1 0 1 00 11 11 1 1 0
0 1 1 0 00 00 11 1 1 1
0 1 1 1 11 11 11 0 0 0
1 0 0 0 00 00 11 0 0 1
1 0 0 1 00 11 11 0 1 0
1 0 1 0 00 00 11 0 1 1
1 0 1 1 11 11 11 1 0 0
1 1 0 0 00 00 11 1 0 1
1 1 0 1 00 11 11 1 1 0 •  Let Count Enable(E ) = 1
1 1 1 0 00 00 11 1 1 1 • FF0: ,always toggle
• FF1:.E
1 1 1 1 11 11 11 0 0 0 • FF2: = . .
   .

0 0 0 0 0 0 00 0 0 11 0 0 0 1
0 0 0 1 0 0 00 1 1 11 0 0 1 0
0 0 1 0 0 0 00 0 0 11 0 0 1 1
0 0 1 1 0 0 11 1 11 0
1 0 1 0
0 1 0 0 0 0 00 0 11 0
0 1 0 1
0 1 0 1 0 0 00 1 1 11 0 1 1 0
0 1 1 0 0 0 00 0 0 11 0 1 1 1
0 1 1 1 1 1 11 1 1 11 1 0 0 0
1 0 0 0 0 0 00 0 11
0 1 0 0 1
1 0 0 1 0 0 00 1 11
1 1 0 1 0
1 0 1 0 0 0 00 0 0 11 1 0 1 1
1 0 1 1 0 0 11 1 1 11 1 1 0 0 •  Let Count Enable(E ) = 1
1 1 0 0 0 0 00 0 0 11 1 1 0 1 • FF0: ,always toggle
• FF1:.E
1 1 0 1 0 0 00 1 11
1 1 1 1 0 • FF2: = . .
1 1 1 0 0 0 00 0 0 11 1 1 1 1
• FF3: = . = .

1 1 1 1 1 1 11 1 1 11 0 0 0 0
 𝐴 0 ′ 𝑄  0
0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0
𝑠
 
0 0 1 0 1 1 0 1
𝐴 1 ′ 𝑄1  ❑ 0 0 1 1 1 1 0 0
0 1 0 0 1 0 1 1
𝑠  0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 1
𝐴 2 ′ 𝑄  2
0 1 1 1 0 0 0 0
1 0 0 0 0 1 1 1
𝑠  1 0 0
𝑄  1 0 1 1 0

𝐴 3 ′ 𝑄  3 1 0 1 0
𝑄′  0 𝑄  0 1 0 1
1 0 1 1 0 1 0 0
𝑠  1 1 0 0   𝑠 0 0 1 1
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1
If s=0 up counter 1 1 1 1 0 0 0 0
If s=1 down counter
Please send
On-Line Assignment  if you have any question or
an e-mail
need any help 

Stay Safe 
Eng. Yasmin Massoud
yasmin.massoud@guc.edu.eg