Subject Name: Computer Architecture

Department: Bachelor of Computer Application

Created By: Dr. Sanjeev Punia

JIMS Engineering Management Technical Campus

48/4, Knowledhe Park – III, Greater Noida - 201306
(Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)
Subject: Computer Architecture (BCA 203)
Topic: Combinational Circuits
Topics to be covered

Logic Circuits
▰ Sequential logic circuits
Asynchronous/Synchronous sequential circuits
▰ Bistable devices
Latch
Flip-Flops
 Logic Circuits

Logic circuits are divided into two classes:

▻ Combinational logic circuits
▻ Output signals only depend on current input signals
▻ Memory less circuits
▻ Sequential logic circuits
▻ Output signals not only depend on current input signals,
but also depend on past output signals Memory circuits
Sequential Circuits

Combinatorial circuit is memoryless.

In a circuit with memory, an output value at tn+1 must be a

function not only of the inputs at tn+1 but also of the outputs at tn.

To achieve this, the circuit must have some feedback

connections from its outputs to its inputs.

A circuit with memory is a combinatorial circuit

incorporating some feedback connections.
Sequential circuit model

x1 z1

... ...
x2 z2
Circuit inputs Circuit outputs
Combinatorial
circuit
xn

yk Memory Yk
device

Present state .. Next state

.
y1 Memory Y1
device
Asynchronous/Synchronous sequential circuits

The timing of the signal in the circuit determine two

types of sequential circuits:

▻ Synchronous
▻ Asynchronous.
 Synchronous sequential circuits

▰ a synchronous sequential circuit, the state can change only at discrete

instants of time.
▰ To achieve that, the circuit uses a timing device, called a clock
generator, that produce trains of periodic or aperiodic clock pulses.
▰ The clock pulses are input to the memory devices so that they can
change state only in response to the arrival of a pulse and only once
for each pulse occurrence.

The operation of the circuit is synchronized with the clock pulse input.
 Asynchronous sequential circuits

▰ a The behavior of an asynchronous sequential circuit depends only on the

order in which the inputs change and can be affected at any instant of time.

▰ There is no timing device in asynchronous sequential circuit (unclocked

memory).
 Bistable devices

A bistable device remains in one of two states indefinitely until

directed by an input signal to change state.
Two stable states:
Q=0 : the device is reset (reset state)
Q=1: the device is set (set state)

Two types:
▻ Latch
▻ Flip-flop
 Latch

Latch: transparency property:

▻ Change state when the input values change

▻ The new output state is delayed only by the propagation time

delays of the gates between inputs and outputs of the latch.

▻ Used to implement the memory part of asynchronous circuits.

 Latch

S Q
Current state

S R Q Q+
R Q’ Next state
0 0 0 0

S 0 0 1 1
Q
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
Q'
R 1 1 0 -
1 1 1 - Indeterminate
Q = (R+Q’)’
Q’= (S+Q)’
 Flip-Flops

A Flip-flop has no transparency property

▻ Has a control (triggering) input, called clock.

▻ The state change only in response to a transition of a clock pulse at

clock input.

▻ Used to implement memory part of synchronous circuits

 Types of Flip-Flops

Four common types of flip-flops:

▻ SR
▻ D
▻ JK
▻ T
Difference between Latch and Flip-flop

▰ The flip-flop can not change state except on the triggering edge
of clock pulse => synchronous

▰ Present and next states in a latch are separated In time by gate

delays, they are separated by clock periods in a flip-flop.
 Flip-flops Triggering

S Q S Q S Q

CLK CLK CLK

R Q R Q R Q

Positive edge-triggered Negative edge-triggered Pulse-triggered

(Master-Slave)
 Flip-flops Triggering

▰ The triangle called dynamic indicator, indicates that the device

responds only to an input clock transition from LOW (0) to
HIGH (1) => Positive edge-triggered

▰ Appending a small circle to the CLK input indicates that the

flip-flop responds only to an input clock transition from HIGH
(1) to LOW (0) => Negative edge-triggered
 SR Flip-flops

S Q S Q S Q

CLK CLK CLK

R Q R Q R Q

Positive edge-triggered Negative edge-triggered Pulse-triggered

(Master-Slave)
D flip-flop

D flip-flop is useful for storing a single bit

D
D Q S Q

CLK CLK
CLK
Q’ R Q

Positive edge-triggered D flip-flop Implementation using SR flip-flop

JK flip-flop

J Q S Q

CLK CLK

K Q’ R Q

Positive edge-triggered JK flip-flop Implementation using SR flip-flop

 Master-Slave flip-flop

Master Slave
S S Q S Q Q
C E E

R R Q’ R Q’ Q’

Master latch works when C=1

Slave latch works when C=0

A pulse-triggered flip-flop consists of two latches, where one acts as a master

and the other acts as a slave => Master-slave flip-flop
Flip-Flop conversions

Implement T-FF using SR-FF

SR-FF T-FF
S R Q Q+ T Q Q+
0 0 0 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 1
1 0 1 1
Expanded state table shows the
1 1 0 -
state
1 1 1 -
transition by the input
Difference between Latch and Flip-flop

Example: Implement D flip-flop using JK FF

excitation table of JK-FF

state 　　　 input

D Q Q+ Q 　　 Q+ 　　 J K
0 0 0 0 0 0 -
0 1 0
1 0 1 0 1 1 -
1 1 1 1 0 - 1
expanded state table of D-FF 1 1 - 0
Thank You !!