Seminar

On
Time Borrowing & Clock skew
Submitted to - Presented by-
Mr. Rajesh Mehra Ruby Verma (101626)
Associate Professor
ME Modular (ECE)
 Outline
Max and Min-Delay

Time Borrowing

Clock Skew

Two-Phase Clocking

Conclusion
 Timing Diagrams
tpd Logic Prop. Delay A tpd
Combinational
A Y
Logic
tcd Logic Cont. Delay Y tcd

tpcq Latch/Flop Clk-Q Prop Delay

clk clk tsetup
thold
tccq Latch/Flop Clk-Q Cont. Delay

Flop
D Q D
tpdq Latch D-Q Prop Delay
tpcq
Q tccq
tcdq Latch D-Q Cont. Delay

tsetup Latch/Flop Setup Time

clk tsetup thold
clk
tccq tpcq
thold Latch/Flop Hold Time
D
Latch

D Q tpdq
tcdq
Q
 Max-Delay: Flip-Flops
clk clk

Q1 D2
F1

F2
Combinational Logic

Tc

tsetup
clk
tpcq

Q1 tpd

D2

t pd  T c   t setup  t pcq 
    
sequencing overhead
 Max Delay: 2-Phase Latches
1 2 1

D1 Q1 Combinational D2 Q2 Combinational D3 Q3
L1

L2

L3
Logic 1 Logic 2

1

2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

t pd  t pd 1  t pd 2  Tc  2t  
pdq

sequencing overhead
 Min-Delay: Flip-Flops
clk

Q1
CL
F1

clk tcd  thold  tccq

D2
F2

clk

Q1 tccq tcd

D2 thold
 Min-Delay: 2-Phase Latches
1

Q1
CL tcd 1,tcd 2  thold  tccq  tnonoverlap
L1

2

D2
L2

tnonoverlap
1

tccq
2

Q1 tcd

D2 thold

Hold time reduced by non-overlap

 Time Borrowing
Time borrowing refers to the time sharing
phenomenon between consecutive clock cycles due to
the transparency of latches.
• In a flop-based system:
– Data launches on one rising edge, must setup before
next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– So flip flop are hard edge device.
 Time Borrowing
• In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next cycle
– So latch- based systems are softer edge device.
 Time Borrowing Example
1
In transparent latches:
2 Time borrowing can
1 2 1
accumulate across multiple
Combinational cycle.
Latch

Latch

Latch
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

In system with feedback:
half-cycle boundary pipeline stage boundary Time borrowing occurs across
1 2 half-cycle, but the entire path
Combinational must fit in one cycle.
Latch

Latch

(b) Combinational Logic Logic

Loops may borrow time internally but must complete within the cycle
 How Much Borrowing?

1 2 2-Phase Latches
D1 Q1 D2 Q2
Tc
tborrow    tsetup  tnonoverlap 
Combinational Logic 1
L1

L2
2
1

2 tnonoverlap
Tc

tsetup
Tc/2 tborrow
Nominal Half-Cycle 1 Delay

D2
 Clock Skew
We have assumed zero clock skew
Clocks really have uncertainty in arrival time
Decreases maximum propagation delay
Increases minimum contamination delay
Decreases time borrowing

• This can be caused by different things, such as wire-

interconnect length, temperature variations, variation
in intermediate devices, material imperfections
 Skew: Flip-Flops
clk clk

Q1 D2

F2
F1

Combinational Logic

Tc

clk
tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1
t pd  Tc   t pcq  tsetup  tskew 
      
F1

CL

clk
sequencing overhead

tcd  thold  tccq  tskew

D2
F2

tskew

clk
thold

Q1 tccq

D2 tcd
 Skew: Latches
Contamination delay and borrow time are affected
by clock skew.
But clock skew does not degrade performance.
Because full cycle is available for computation.
1 2 1

D1 Q1 Combinational D2 Q2 Combinational D3 Q3
L1

L3
Logic 1 L2 Logic 2

1

2
 Skew: Latches
2-Phase Latches

t pd  Tc  2t  
pdq

sequencing overhead

tcd 1 , tcd 2  t hold  tccq  t nonoverlap  tskew

Tc
t borrow    tsetup  tnonoverlap  tskew 
2
 Two-Phase Clocking
If setup times are violated, reduce clock speed
If hold times are violated, chip fails at any speed
Working chips are most important
Analyzing clock skew difficult
An easy way to guarantee hold times is to use 2-phase
latches with big non-overlap times
 Conclusion
• The simultaneous application of clock skew scheduling
and time borrowing in order to increase the circuit
performance has been presented on single-phase level-
sensitive circuits.

• For flip-flop based synchronous circuits, time borrowing,

thus a combined effect with clock skew scheduling, is not
feasible.
THANKS