AREA EFFICIENT DESIGN OF 4-

BIT CARRY SELECT ADDER

WITH LOW POWER
 ABSTRACT
 Adder is an vital operation in ALU. Out of Many existing adders,
Carry select adder have much significance. In this paper we
proposed CMOS Carry select adder with low area as well as low
power. We have designed a cell such that it can produce multiple
outputs and this is what lead to the optimization. Universal gates
like NAND and NOR also used instead of using basic logic gates
like AND and OR has lead to optimization. Half sum generation
unit has been optimized from 64 to 46 transistors. In Carry unit
with zero carry input block transistor reduction is from 36 to 24.
Carry unit with one carry input block there was limited reduction
in transistor count from 42 to 36. Carry unit block has been
optimized from 48 to 32 transistors. Sum unit block has not given
us any scope to do optimization. Total transistor count reduction
for 4-bit is from 230 to 178 with existing design and in equal
proportion optimization is possible for N-bit.
CONTENTS
 Objective
 Carry select adder cell
 Methodology
 Literature review
 Proposed Carry select adder cell using STATIC CMOS
 Schematic design of Carry select adder cell
OBJECTIVE
 Design an Area & Power efficient Carry select adder with
respect to number of transistors by using STATIC CMOS logic.

 Implementation of Carry select adder with respect to 4-bit .

 In this paper we study efficient implementation of Carry
select adder, considering the logic style of STATIC CMOS
logic .

 We show that it is possible to implement Carry select adder

by taking less number of transistors and also with high Speed.

 For any word lengths, Carrry select adder that we have

designed can be implemented and will be efficient with
respect to Area and Speed.
CARRY SELECT ADDER CELL

Used to add two binary numbers.

 It has two parts of Carry.
Carry in is ‘1’ and Carry in is ‘0’.
Above together will form Carry output.
It does have sum output.
METHODOLOGY
 Design is implemented in Full Custom.
 Supply voltage is 1.8v.
 Tanner tools are used with version 15.
 S-EDIT for Schematic Design.
 T-SPICE for Simulation.
LITERATURE SURVEY
 Basant Kumar Mohanty’s carry select adder is based on
logic gates.
 They have used the gates like XOR,AND and OR. Total
number of gates required are 33.
 Carry select adder which we designed is based on gates
as well as cells.
PROPOSED CARRY SELECT ADDER
USING STATIC CMOS LOGIC
 XNOR block.
 HSCG BLOCK.

 Carry when carry input is ‘0’.

 Carry when carry input is ‘1’.

 CARRY BLOCK.

 SUM BLOCK.

 Block diagram.
CIRCUIT OF EXISTING & PROPOSED
XNOR
HSCG BLOCK
CARRY OUTPUTS FOR EXISTING &
PROPOSED WHEN CIN=0
CARRY OUTPUTS FOR EXISTING &
PROPOSED WHEN CIN=1
CARRY OUTPUTS FOR EXISTING &
PROPOSED
SUM OUTPUTS FOR EXISTING &
PROPOSED
BLOCK DIAGRAM OF 4-BIT CSA
 COMPARISON OF AREA IN TWO
DESIGNS

Basant Kumar Proposed

(Transistors) Mohanty

4-bit 230 178

 CONCLUSION

 Nor, Xnor, Nand are used in our Design, these are our
own Designed blocks we came across in our Design
process instead of using basic logic gates or universal
gates.

 STATIC CMOS has the disadvantage of taking more

number of transistors but we were able to surpass the
Basant Kumar Mohanty design.
 Design which we presented can be very affectively
suitable to larger word lengths.
 FUTURE DIRECTIONS
 This project is implemented for Carry select adder using
STATIC CMOS logic, since it has the advantage of full
output voltage swing it will be beneficial when
technology is scaled down.

 Carry select adder which we Designed has less transistor

count , now since we have given our own architecture
any one can design our blocks using other logic styles.
THANK YOU