Chapter 11

ULSI (nano) fabrication

Girija 1
Introduction
Generations of IC technology (generally based on gate length)
Small-Scale Integration (SSI),
Medium-Scale Integration (MSI),
Large-Scale Integration (VSI),
Very Large-Scale Integration (VLSI) and
Ultra Large-Scale Integration (ULSI).

ULSI (below 1micrometer) generation are

Submicron technology,
Deep submicron technology (90 nm to 65 nm) and
Ultra deep submicron technology (45 nm to 32 nm)
ULSI fabrication is complex and needs new fabrication techniques and equipments.
ULSI fabrication issues are

Drain junction Leakage current,

Breakdown control,
Punch through,
Short channel effects
Hot electron generation,
MOS transistor VT fluctuation,
Contact resistance,
Parasitic resistance and
Capacitance and
Mismatch of MOS transistors threshold voltage
Girija 2
Fabrication issues
ULSI processing needs low thermal budget (temperature multiply by time).
The ideal condition of low thermal budget is low temperature and short time.
Presently, ULSI processes cannot be done in ideal thermal budget due to non-
availability of equipments, processes technique and requirements of material.
ULSI fabrication equipments
Some existing equipments and process are modified for ULSI fabrication. New
precursor (recipe) and
New MOS structures are coming up to meet the challenges of ULSI fabrication.
For low thermal budget process, Rapid Thermal Processing (RTP) equipment is
introduced (it conceptualized from Rapid Thermal Annealing (RTA) system).
Wafer throughput in RTP (and RTA) equipment due to single wafer processing.
Derivatives of RTP
RTP is used for oxidation then is called “Rapid Thermal Oxidation” (RTO)
RTP is used for CVD then is called “Rapid Thermal Chemical Vapour Deposition”
(RTCVD).
In RTO is used for annealing process then is called RTO-RTA.
RTCVD followed by RTA annealing then is called RTCVD-RTA.

Girija 3
Silicon dioxide
ULSI require thin silicon dioxide gate film (~ 70 Å gate for 0.25 µm of MOS) i.e.
a few atomic layers (i.e. fundamental limits of silicon dioxide).

Decrease in oxide thickness leads to exponentially increase of gate leakage

current.
To avoid the high k gate dielectric materials such as silicon nitride or oxynitride
(SiOxNy), zirconium oxide (ZO2), hafnimum oxide (HfO2), aluminum oxide (Al2O3)
and lanthalum oxide (La2O3) dielectric are coming.

To grow thin oxide dry oxidization is carried in the moisture free oxygen gas from
700 to 1000°C temperature range for short time.

ULSI requires good quality and uniform thin oxide film across (0.25 µm MOS
needs ~ 70 Å gate thicknesses with not more than 7 Å thickness variations across
the wafer, otherwise, VT will vary across the wafer.

Defect density in the oxide should be > 0.5/cm2 to keep leakage current in limit.

Girija 4
 Schematic of RTO system and heating cycle
Heating system
Oxidation in RTA and
Input load Output load lock properties of oxide
lock
Reaction
O2 = O + O
Wafer
O + O 2 + O 2 = O3 + O 2
Processing chamber O + O3 = 2O2
Gas delivery system
O3 = O + O 2
Activation energy ~1.44
Oxidation time
N2 gas Heated in oxygen gas Less oxide charges compare
Temperature ºC

1400
1200 Anneal in N2 gas to furnace oxidation
High charge-to-breakdown
900 Ramp down
Ramp up 80 C/cm2 compare to
600
breakdown 20 C/cm2 in the
300 0 60 120 180
Time in seconds furnace oxidation
Girija 5
 Dielectric deposition

Use of dielectric A few ULSI fabrication issues

1.Electrical isolation Uniform wafer heating and temperature
2.Surface passivation
3.Gate wall passivation measurement in RTP over large diameter
4.Diffusion mask wafer (800 mm and above).
5.Gate electrode Interlevel
Lithography resolution,
dielectric (ILD) between metal
Properties of dielectric Exposure systems,
1.Uniform film
Etching,
2.Uniform film thickness
3.Good step coverage Film deposition in holes,
4.No voids
Multi level wiring,
5.High dielectric constant
6.Free from contamination Contact etc.

Girija 6
Silicon dioxide deposition
Silicon dioxide deposition by RTO process
Pyrolysis of Tetraethoxysilance (TEOS) precursor.
Si(OC2H5)4 → SiO2 + 2H2O + 4C2H4

Below 800°C, oxide deposition rate is slow but above significantly increases to
1000Å/min.
Good for dielectric film in IDL purposes were aluminum metal is not present.

Silicon dioxide is also deposited with silane precursor added with O2 or N2O2 gas
SiH4 +2N2O2 → SiO2 +2N2 +2H2O
Silane and oxygen reaction takes place at temperature (300 to 450°C), but at this
temperature, particulates generate so generally avoided.
At temperature around 800°C, silane is mixed with nitrous oxide a good quality and
stoichiometric oxide film is formed.
This process is almost 100 times faster than the furnace thermal oxidation, but
cannot be used in IDL if aluminum is present.

Girija 7
Silicon dioxide can also be deposited using TEOS by CVD
techniques,
Not used for ILD due to high deposition temperature, porous oxide and
water absorbing property that corrodes metal known as “contact poisoning”.
High aspect ratio with good step coverage by APCVD and Sub-atmospheric CVD
(SACVD) techniques, precursor used TEOS between 250 to 400°C.
Believes that in the CVD reactor, TEOS decomposes and releases ozone
and that in turn reacts with TEOS and form silicon dioxide.
Deposition rate of silicon dioxide depends on ozone conc. and temperature.
Deposition rate increases till 1% of ozone conc. and, thereafter it declines.
Deposition rate also increases in the range of 100 to 250°C and good quality of
oxide film is obtained with higher temperature.
Deposition rate is 30% higher on bare silicon than on the silicon dioxide.
To prevent contact poisoning, combination of PECVD and CVD are used.

Girija 8
TEOS by plasma assisted (PECVD) technique
TEOS reacts with oxygen even below 400°C
Si(OC2H5)4 + O2 = SiO2 + by-product
Good quality of silicon dioxide
Good step coverage is obtained.
Deposition is more at metal line edge than the other places that creates void
and conformal film deposition-etch-deposition (dep-etch-dep) process is used.
Using N2O reduction film suffers from poor step coverage, but it can be
improved by high density plasma process

Silicon dioxide deposition (rate Å/min) Step coverage and surface migration
using TEOS in RTO process
104
Deposition
Rate in Log (a) (b) (c)
102
Scale (a) Valley/trench structure

100 (b) Step coverage due to good surface migration

700 800 900 (c)Step coverage due to bad surface migration
Temperature (⁰C) Girija 9
Quartz target sputtered deposition
Quality oxide deposition in narrow gaps and undercuts high density plasma (HDP)
sputtering at low temperature is used.
For high deposition rate, less plasma radiation, less compressive stress with no
particulates, substrate biased HDP technique may be used for ULSI.
 

Spin-on-Glass (SOG)
SOG is coated on the wafer and then heating (curing) silicon dioxide is obtained.
Method is simple, good step coverage and low cost, but not used in ULSI.
Types of SOGs
Inorganic based and Organic based.
Both SOGs can be modified by adding B or P called modified SOGs. But absorbs
water and poisons metal, and it has low dielectric constant (3.0 to 3.6), compare to
4.5 dielectric constant by furnace oxidation.
Inorganic (silicate) SOG is thermally stable, fills narrow gap, absorb less water
but suffers from shrinkage and cracks.
 Introducing >4% of phosphorous it becomes softer and less stressed, but
absorption of water and results metal poisoning.
Organic SOG (siloxane) oxide absorbs less water, carbon impurity, poor
mechanical strength, low melting point (400°C) and can’t stand plasma exposure.

Girija 10
Nitride deposition
Use
LOCOS, oxidation mask, passivation of IC, diffusion barrier, and gate for Metal
Nitride-Oxide Semiconductor (MNOS).
Presently, LOCOS is not popular in ULSI, as it consumes Si due to bird beak.
Deposition
1.For submicron MOS device, RTCVD is used but lesser film thickness.
Good film is obtained by silane with ammonia gases (1:120), at ~ 800°C with
deposition rate (~ 100Å/min).
3SiH4 +4NH2 → Si3N4 + 12H2
Nitride can also be deposited by APCVD at 700 to 800°C.

2. (SiH2Cl2) and ammonia gases by LPCVD technique at 700 to 800°C.

But in the RTCVD NH4Cl particles deposits on the cooled places of the chamber
SiH2Cl2 + 10NH2 → Si3N4 + 6NH4Cl + 6H2

Girija 11
Silicon deposition
1.Polysilicon deposition
Use
MOS gate, short electrical connections, resistor, barrier of metal diffusion and
metal silicide formation.
Deposition
Pyrolysis of silane gas
SiH4 → Si + 2H2
Generally, silane gas is diluted either with nitrogen or argon gas. The surface
quality depend on silane and nitrogen or argon gases ratio.
For reasonable deposition rate, pyrolysis of TEOS is done in RTP at
above 700°C for a very short time.
Polysilicon surface is smoother when polysilicon deposition is done by
RTCVD process at high temperature.

Girija 12
Epitaxial (Epi) silicon deposition
Crystalline film deposited either on the same type of substrate material
(homoepitaxy) or on the different type of substrate material (hetroepitaxy).
CVD Deposition at high temp. ~1000°C not suitable for submicron.

To deposition crystalline Si film on the Si wafer is called “epitaxial film

deposition or grown”.

Advantages
Doping profile and doping conc. in the film can be tailor according to the
requirements. Thus it is better process than diffusion and ion-implantation.
Epi film deposition rate is much higher on the bare silicon than silicon oxide
and silicon nitride and that leads to better planarization.
Epi film prevents latch-up, submicron electrical isolation, good planarity property,
and good buried layer quality.
Disadvantages
High temperature process introduces unwanted auto-doping, over buried layer
washout and patterns shift distortion.

Girija 13
Epitaxial deposition techniques
Silicon atoms loosely adhere to substrate, and migrate on the substrate (surface
migration) that forms crystalline film.
RTCVD (~ 500°C) useful for ULSI as there is no significant change of junction
depth, auto-doping and doping profile.

Deposition methods
Deposition is done in ultrahigh vacuum chemical vapour deposition (UHVCVD)
system below 10-9 torr.
Silane (SH4) is preferred over Si2H6 because of low deposition temperature is
around 100°C at 10-6 torr.
For doping diborane (B2H6) or phosphine (PH3) gases are used.

Girija 14
2. Molecular Beam Epitaxy (MBE) technique
MBE is complicated than the UHVCD reactor, but precise control over epitaxial
thickness and doping.
MBE deposition solid silicon is evaporated by e-beam at 10-11 torr from 500
to 900°C.
Doping can be done by evaporating silicon and dopant simultaneously (in situ).
Deposition is done by silicon vapour has cluster formation and spitting problems.
To overcome these defects, gaseous source (GS) is used.
GS is similar to UHVCVD and called GSMBE, except that GSMBE is a cold wall
system (UHVCVD is hot wall system).
Deposition by GSMBE may be future technique for deep submicron device.

Spectrometer ShutterWafer Mass spectrometer Gas delivery system

ports
Load lock
Dopant & Load lock Exhausts system
gaseous
sources
Exhaust
ports Turbo-
Rotation system molecular
Gas ports pumps
Vacuum port Rotary pump Rotary pump

Girija 15
Metal deposition
Use
Electrical contact and electrical wiring.
It should have minimum possible resistance and capacitance, and must
follow Ohm’s law.
Multilevel level wiring.

Deposition techniques
Physical Vapour Deposition (PVD) and Chemical Vapour Deposition (CVD)

These two techniques can be extended for deep submicron device

fabrication with some modification or inventing new technique.
 

Girija 16
Aluminum deposition
Sputtering technique has advantages of
Uniform deposition, control thickness and pre-deposition wafer cleaning.
Aluminum reflow (plugging of contact holes).
By the RTA technique, Al reacts and damages the barrier layer when heated.
Excimer laser heating technique, has no damage due to short exposure time.
UV laser needs intense light as aluminum due to high reflectivity of Al.
High laser beam heating technique, Al ablation and reacts with Ti that results
in a high resistivity.
High temperature in situ reflow of aluminum.
Al deposited and then put to ~ 500°C for a few minutes at 1 x 10-8 torr, but for
longer time a robust TiN barrier layer is needed.
For Al wetting with TiN, a layer of Ti or TiSi2 or Si is sandwiched.
Low and high aluminum plug deposition technique.
I this technique, a thin Al film is sputtered as a seed at low temperature and then
Al is deposited around 450°C.
This Al seed provides surface diffusion for second deposition Al at high temp.
This technique needs less stringent barrier film.
Low temp. 350 to 400°C with high pressure ~ 600 Mpa plunges hole.
Al plugging depends on shape and aspect ratio of holes.

Girija 17
Aluminum can also be deposited by CVD technique
TIBA + H2 = DIBAH at 40 to 50°C produces
DIBAH + H2 = AlH3 + 2C4H8 decomposes at 150 to 300°C
AlH3 = Al + 3/2 H3 decomposes
Procedure has low Al resistivity (~ 2.8 µΩ-cm) close to bulk when TiN barrier
layer is used in between aluminum metal and silicon.
Disadvantages
(1)low vapour pressure,
(2)less utilization of TIBA,
(3)explosive,
(4)prone to fire,
(5)violent reaction with water,
(6)copper cannot be deposited simultaneously to check the Al electromigration.
Remedy
Half of the Al thickness is deposited using TIBA precursor and rest half
Al is deposited by sputtering of 2.5 % copper contained target
aluminum film (Dimethyl Aluminum Hydride (DMAH) along with
Cyclopentadienyl Copper Triethylphosphine (CpCuTEP) precursors)
Low deposition rate restricts for Al deposition for ULSI applications.

Girija 18
Tungsten (W) deposition
 W film resistivity is ~ 4 times > Al film.
Mostly used for vias (holes) plugging and short connections.
Deposited
CVD technique, 400 to 500°C in presence of WF4 precursors
WF6 + 3H2 = W +6HF (hydrogen reduction)
2WF6 + 3Si = 2W +3SiF4 (silicon reduction)
WF6 + SiH4 = W + SiF4 + 2HF + H2 (silane reduction)
2WF6 + 3SiH4 = 2W + 3SiF4 + 6H2 (silane reduction)
WF6 + 2Al = W + 2AlF3 (aluminum reduction)
2WF6 + 3 Ti = 2W + 3TiF4 (titanium reduction)
Al and Ti, consumes Si ~ 20 nm and that leads to junction leakage.
TiN or TiW barrier reduces leakage current and provides good adhesion of W with
SiO2.
W plugging by hydrogen reduction, suffers from selective nucleation (growth).
Increase selectivity, uniform plugging and better adhesion TiN or TiW layer is used.
W plugging can be achieved by W and TiN deposition etching by RIE except
from the contact areas and again W is deposited by dep-etch-dep technique.
TiW barrier layer is not used because of end point detection problem.
Girija 19
Titanium deposition
Ti is deposited at 400°C by ion sputtering technique or ECR techniques.
ECR-enhance CVD process shows good results for submicron device,
But by CVD process suffers from electronegative and thermodynamically unstable.
Copper deposition
Cu has less resistivity than Al and there is no electromigration.
Cu is deposited by damascene process (easy patterning and avoiding oxidation).
Better quality, low resistivity 2 µΩ-cm (bulk resistivity1.9µΩ-cm) and reasonable
deposition rate can be obtained by hydrogen reduction of Cu(hfac) in CVD.
Cu(hfac)2 + H2 = Cu + 2H(hfac) at 350 to 450°C,
Recently, copper for electrical wiring by electroless plating is under study.
To deposit copper, CuSO4 and formaldehyde chemicals are used.
Cu2+ 2HCHO + 4OH- = Cu + 2HCOO- + 2H2O +H2
Nickel deposition
Nickel deposit in submicron contact and plugs very well.
Ni2 + (H2PO2)- + H2O = Ni + 2H+ + H(HPO3)-
Easy deposition, low temperature process and thicker metal can be deposited
with less stress. Presently, it has disadvantage of contamination, but future
research may overcome this disadvantage.

Girija 20
Silicide/polysilicide and nitrides film deposition

Use
(1)To promote good electrical connection
(2)Holes plugging for electrical connection and
(3)Barrier layer for electromigration (especially for gate polysilicon, source and
drain contacts).
Ti, Co, Ta, and W metals are used for silicide formation.
The resistivity of TiSi2 and CoSi are ~ 10 to 15μΩ-cm.
Silicide is used for self-align process
Presently, these materials are used for submicron device application, but it
has reached to its limits due to its thickness variation and thermal stability.
Deposition technique
Deposition is done either by the CVD or by the sputtering techniques.

Girija 21
Self align silicide process

Si Oxidation

Poly deposition
Si

Silicide deposition/formation
Si

Si Source and drain formation

Source and drain implantation

Si

Oxide deposition, contact window opening

Si

Metal deposition and pattering

Si

Girija 22
TiN deposition
Use
Barrier for Al electromigration, to check W reaction with silicon and better electrical
contact with silicon.
Deposition techniques
Reactive sputtering technique or CVD technique.
In the RF reactive sputtering TiN target is used.
In MOCVD molecular-organic chemical vapour deposition from 400 to 700°C.
6TiCl4+ 8NH3 = 6TiN + 24 HCl + N2 (ammonia reduction)
2TiCl4 + 2NH3 + H2 = 2TiN + 8HCl (ammonia reduction)
2TiCl+ N2+ 4H2 = 2TiN + 8HCl (H2 & N2 reduction)
For higher TiN deposition rate ~ 0.5% of chlorine remains in TiN film,
Ammonia gas reduction ~ 5% of chlorine is used that leads to metal corrosion.
Metal-organic precursors, such as Tetrakis–(dimethylamido)-Ti (TDMAT) or
tetrakis–(diethylamido)-Ti (TDEAT) mixed with ammonia gas (NH3),
6Ti[NCH3)2]4 + 8NH3 = 6TiN + 24HN(CH3)2 + N2 (below 450°C)

Girija 23
TiN deposited by Metal-organic precursor has low density, unstable, high
resistivity due to presence of C and O2 and less step coverage in high aspect
ratio.

Better step coverage is reported by TDEAT precursor with low resistivity (180
µΩ-cm) against 500 µΩ-cm obtained by TDMAT precursor.

Plasma assisted TiN deposition by NH3 reduction around 550°C has been
explored. By this deposition procedure TiN contains 1% of Cl.

Good quality TiN film with 40 µΩ-cm can be deposited by electron cyclotron
resonance (ECR) technique using TiCl4 precursor.

TiN can be deposited by ECR technique with TDMAT precursor at lower

temperature (<400°C) with resistivity ranging from 200 to 300 µΩ-cm.

TiN contact with heavily doped boron (n+) or phosphorous (p+) silicon results in
high resistance. To overcome this problem, around 40 nm Ti is deposited prior to
TiN deposition.

Girija 24
TiSi2 deposition
Sputtered from Ti and heated in RTP from 620 to 680⁰C and followed by 750⁰C
Ti + 2Si = TiSi2 (C-49)
TiSi2 (C-49) = TiSi2 (C-54)
Co deposition is same as Ti deposition.
TiSi2 deposited by CVD has 3 to 4 times lower resistivity than WSi2 and
TaSi2.
At 650 to 700°C in LPCVD reactor,
TiCl4 + 2Si + 2H2 = TiSi2 + 4HCl
TiCl4 + 2SiH4 = TiSi2 + 4HCl + 2H2
TaSi2 deposition
Deposited by standard sputtering process and can also be deposited by CVD.
In the LPCVD technique,
Ta5Si3 + 7 Si = 5 TaSi2
Or byTaCl5 precursor by the same process.
It is not uniform and develops notches and damages the gate oxide. For this
4TaCl5 + 13Si = 4TaSi2 + 5SiCl4
Popular deposition at 650°C in LPCVD, but damages gate oxide similar way.
TaCl5 + 2SiH2Cl2 + 2.5H2 = TaSi2 + 9HCl
5TaCl5 + 3SiH4 + 6.5 H2 = Ta5Si2 + 25HCl at 600°C
Girija 25
TaSi2 and TiSi2 silicides and displacement reaction
Silicide brings low contact between the metal
4TaCl5 + 13Si = 4TaSi2 + 5SiCl4
TiCl4 + 2Si + 2H2 = TiSi2 + 4HCl
Displacement reaction occurs.
TaCl5 and TiCl4 consumes 150 to 250 nm and 300 to 600 nm of silicon
respectively.
In addition, while of silicide formation, defects are created in the silicon that
enhances the source and drain the junction depth.
Can be controlled the source and drain implantation after silicide formation.
WSi2
Both CVD and sputtering techniques are used.
Low resistance WSi2 polycide is made on top of the polysilicon gate to reduce
the gate resistance.
In the CVD process, from 300 to 400°C with WF6/SiH4 more than 10 to get good
WSi2 film.
WF6 + 2SiH4 = WSi2 + 6HF + H2
Deposition from 500 to 600°C by dichlorosilane (SiH2Cl2) reduction, which has 4
to 5 times faster deposition rate and better step coverage.
WF6 +3.5SiH2Cl2 = WSi2 + Girija
1.5SiF4 + 7HCl 26
 Lithography
Lithography resolution mainly depends on (1) exposure wavelength, (2) exposure
system, (3) numerical aperture, (4) pattern placement, (5) photoresist (resist)
resolution, (6) depth of focus of exposure system, (7) modulation of wafer surface.

Optical lithography
The optical lithography is simple, low cost, easy to maintain, high field of view and
wafer throughput is high.
There are three modes (1) contact mode, (2) proximity mode and (3) projection
In the contact mode, are made intimate contact pressure range from 0.05 atm
(soft contact) to 0.3 atm (hard contact) between the mask and wafer .
Resolution better than 0.5 µm with I-line (λ =365 nm).
The contact mode introduces defects in mask and wafer in each cycle of contact.
In addition, the resolution variation comes due to the wafer surface modulation
and wafer bow.
Despite of all these disadvantages, the contact mode is used for submicron
devices lithography till today.
In proximity mode there is gap between the mask and the wafer of a few
micrometers.
Not used in submicron lithography because of poor resolution.

Girija 27
Presently, the optical projection mode is used extensively.
The numerical aperture and depth of focus is optimized for better resolution.
Three types of optical projection systems. (1) reflection optical projection,
(2) refraction optical projection and (3) catadioptric projection systems
(combination of reflection and refraction projection) Catadioptric system one can
resolve up to 0.4 µm.
Lithography Resolution
Depends on optical system, photoresist , mechanical system, and exposure
system, temperature, developer and starring while developing.
In submicron device technology, the alignment of mask - wafer is more crucial.
Alignment inaccuracy comes mainly due to personal errors, exposure system,
mask aligner stability, machine vibration and floor vibration, and lithography
Alignment inaccuracy brings the resolution down.
Optical resolution
I-line has resolution up to 0.4 µm and 0.3 nm with 248 nm wavelength of excimer
laser light source (KrF laser).
By mask modification, (mask engineering).

Girija 28
Phase shift techniques on mask to improve
resolution (mask engineering)
Mask
Amplitude at 180° Phase shift
mask

Amplitude at wafer
Light
amplitude

Intensity at
wafer

Girija 29
Photoresist resolution
Resolution also depends on contrast of the photoresist (material property)
And Modulation Transfer Function (MTF) due to imperfection of optics.
PR contrast mainly depends on wavelength of light, pre-bake and post-bake
temperature, developer temperature, concentration of developer, and
underlying material.
PR contrast is experimentally determined the responses to the light intensity
by exposing light energy and developing in step measuring PR thickness
keeping all other lithographic parameters constant.

Fraction of PR remaining
Fraction of PR remaining

Positive PR Negative PR
1 1

Q0 Qf Qf Q0

00 100 00 100
Exposed Dose (mJ cm-2)

Girija 30
 MTF or Critical MTF (CMTF) tells about the optical property and imperfection of
the
lens projection system.
MTF defines the light contrast in the aerial image that falls on the PR.
MTF of an optical system = (I Max- IMin ) /(I Max+ I Min )
Where, Imax maximum light intensity and Imin minimum light intensity of image .
The image formed by projection system does not represent the ideal
representation of mask in terms of light distribution (on PR).
The diffraction of light and optical system imperfection both distort the ideal
representation of mask.
To get maximum possible resolution, the ideal image of mask is needed, hence
Optical system is corrected for diffraction (diffraction limited” optical system).
The imperfection of optical system cannot be corrected beyond a certain point.

The Critical MTF (CMTF)

Q0 is the first exposure dose of light and Qf is the last exposure dose of the light.
The typical CMTF value for g-line (or i-line) is around 0.4.

Girija 31
A typical exaggerated light interference effects within the
positive PR
When wafer is exposed, a part of light reflects back from the PR/silicon interface
and interferes with the incoming light that manifests standing interference.
After PR is development the side wall modulation of the PR decreases resolution.
It is more prominent in thick PR. Therefore, thin PR coating is used for ULSI.

centre of transparent pattern in the mask

Opaque pattern in
mask
PR
thickness Less exposure due to bright
fringe
Extra exposure due to bright fringe

Girija 32
Electron beam lithography
Electron wavelength below 1 angstrom, beam spot size > 0.1 µm and NA ~0.01
with 10-15 keV.

e-beam wavelength is ~ 400 times shorter than I-line and NA is ~ 50,000

shorter than 100 X.

It is used for optical and X-ray mask fabrication and “Direct Writing on Wafer”
for ASICs

e-beam exposure has two scanning modes (1) raster scanning mode and (2)
vector scanning mode.

Girija 33
New types of e-beam
Mask for electron beam projection system
Quartz plate

Chrome film CsI film

High resolution and high throughput is obtained by 1:1electron projection system. A

quartz plate has chrome and CsI films. Illuminating by Intense UV light interacts with
CsI and generates electrons. These electrons are accelerated towards the wafer
and expose the resist. But CsI film has short life. But works well for better
throughput with high resolution. It is under development stage.

Electron wafer exposure projection system

UV light

Mask

Electrons
Wafer
X-Y stage
Girija 34
Membrane Electron beam lithography system
Electron gun
Electromagnetic alignment coil
Electromagnetic first coil (condenser lenses)

Blanking plates
Electromagnetic second coil (condenser lenses)
Pattern Aperture
generator
Electromagnetic final coil (condenser lenses)
and
computer High Vacuum system
control Silicon membrane mask
systems Resist coated
Wafer on X-Y stage
silicon membranes
Thick silicon opaque and transparent to silicon membrane to e-beam.
Two complimentary masks are used for total exposure
Generally, the distance between the mask and wafer is kept around 0.5 mm.
It is in developing stage.

Girija 35
 Stencil Electron beam lithography system
Electron gun
Electromagnetic alignment coil
Electromagnetic first coil (condenser lenses)
Blanking plates
Electromagnetic second coil (condenser lenses)
Pattern
generator Stencil
and Electromagnetic final coil (condenser lenses)
computer Port for high Vacuum system
control Silicon Mask
systems Resist coated wafer
X-Y stage

The stencil mask contains several apertures of different shapes.

Electrons are passed through the transparent patterns and expose the wafer.
The size and positioning of the image are controlled by the electrostatic lenses.
Under development stage.

Girija 36
Electron resist resolution
Electron lithography resolution is of~ 0.1 µm, but degrades due to NA,
scattering machine stability, alignment accuracy, mask alignment stability,
vibration of machine and floor vibration and lithography process.
Negative resist swells while developing, leads to adhesion loss, undercut and
prevents etching in between the patterns.
For better resolution more exposure (around 25%) needs in denser patterns
than an isolated below 0.5 µm pattern (can be expose by e-beam).
Scattering of electrons depends on the electron beam energy, thickness of
resist and material below the resist.

Electron
beam

Electron trajectory
inside the PMMA
PMMA

Girija 37
X-ray lithography
X-ray is even transparent to organic material, and dust that reduces the defects
X-ray has small wavelength, large depth of focus, high resolution (around 0.2
µm) and placement accuracy (around 0.03 µm).
X-ray mask is complex to fabrication, fragile and needs mask engineering.
X-ray wavelength is in the order of a few Angstrom,
Error in X – Ray lithography
Due to point source deviation ∂R, if R increases ∂R increases and ∆ increases.
These variation is corrected by mask engineering while mask fabrication.

To overcome the point source projection

S
X- ray source mode is developed. A full mask is
Palladium illuminated by the extended X-ray source
Beryllium and patterns of mask are projected on
window X-rays the wafer by combination of convex and
D concave mirrors. Generally, laser
Mask induced plasma is used to produce soft
g
X-ray, which as less radiation effect on
wafer. This projection X-ray system is in
Wafer R δR developing stage.

Girija 38
X-ray mask fabrication sequence
X-ray mask is made of Au film patterns on the silicon membrane. X-ray is
opaque to gold film; but it is transparent to thin silicon membrane.

Silicon wafer
Gold film

Gold
patterning

Silicon micromachining

Glass ring
Silicon wafer

Plasti Gold Silicon

c patterns membrane

Girija 39
Etching
For ULSI device, high etch rate, high selectivity and perfect anisotropic etching
are imperative.
The uniform etching encounters with two major issues:
(1) Aspect Ratio-Dependent Etching (ARDE) and
(2) Pattern density variation. Closely placed (high density) patterns than the isolated
pattern of identical sizes (called “micro-loading”).

Wet etching
High selectivity, uniform etching, easy process, less cost, and high throughput.
Below 1.5 µm is not recommended and restricts ULSI due to isotropic etching
There are two techniques used for wet etching:
(1) Emersion (dip) technique and
(2) Spray technique.

Girija 40
Silicon dioxide etching
To keep constant etchant rate pH value is maintained by adding NH4F.
Silicon dioxide can be etched submicron patterns using spray etching technique.
(If side etching walls are passivated by hydrogen atoms)
SiO2 + 6HF = H2SiF6 + H2O
H2SiF6 + H2O = SiF4 + 2HF

Presently, the dry etching technique is used for submicron silicon dioxide etching and
it is also faster oxide etching.

Silicon etching
Silicon first converts into silicon dioxide and then it dissolves in the solution.
Si + HNO3 + 6HF = H2SiF6 + HNO2 + H2O + H2
Presently, silicon is etched by dry etching process using CF4 precursor gas but
etch rate of silicon and silicon dioxide is almost same.
To increase the etch rate of silicon with respect to SiO2 around 12% of oxygen
is added into the CF4 gas

Girija 41
Polysilicon etching
In KOH chemical around 80°C (wet etching).
After polysilicon etching, wafer is treated with HCl to remove the potassium ions.
Selectivity between polysilicon and silicon dioxide is high.
Silicon nitride etching
Heating in 85% in H3PO4 ~ 180°C is for silicon nitride etching.
PR cannot be used as a mask due to high temperature process.
It has high selectivity between silicon nitride and silicon dioxide.
The etch rate of CVD deposited silicon nitride is ~ 100Å per minute as against a
few angstrom etching of thermally grown dioxide.
For global removal of silicon nitride from the wafer is the best option.
In present days, nitride is etched by dry etching technique.

Girija 42
Dry etching
Dry etching has limitation of deep etching and micro-loading effect, especially for
denser patterns.
Below 0.5µm and for deep submicron etching needs improvised technique.

Dry etching categories

1. Physical etching technique (sputtering)

2. Reactive ion etching, highly reactive radicals are generated in the plasma and
these radicals react with material and remove material.
3. Chemical-physical etching, combination of both physical and reactive ion etching

Girija 43
Silicon dioxide etching
Reactive fluorine atoms react with the silicon (or its compound) and produce volatile
product,
SiO2 + 4F = SiF4 + O2
If O2is added into the CF4 gas the silicon etch rate and silicon dioxide increase by
12% and 20% respectively, but decreases aterwords.
Reasons
(1)H2 reacts with F and form HF that reduces concentration of F,
(2)CFx reacts with SiO2 and forms SiF4, CO, CO2 and other products,
(3)CF4 reacts with H2 and forms either carbon or hydrocarbon polymer and that
passivate the silicon surface and reduces the F concentration and that in turn
reduces the silicon etch rate.
CF4 +SiO2 =SiF4 + CO + CO2+ COF2
CF4 + Si = SiF4 + C + CFy + CHxFy
CHF3 and combination of (CHF3+CF4) are also used for silicon dioxide etching.

Girija 44
Selectivity depends on
(1)Etching should be thermodynamically favorable for reaction between etchant
and etch material, and
(2)Reactant product should be volatile in nature and exhausted immediately.
Etch profile is very important in ULSI, especially for high aspect ratio.
In dry etching the horizontal etching (undercut) also take place.
To reduce the horizontal etching, ions oblique angles etching is minimized.
In deep etching, side wall undercut is protected from reactant product SiBrxHy
Where Hbr is a reactive product.
In ULSI micro-loading effects etching in aspect ratio dependent etching is
(referred to as ARDE).
Isotropic and anisotropic etching
Veridical Ions Ions

a b
Isotropic etching Anisotropic etching

(a) Isotropic due to vertical ions strike, (b) anisotropic etching due to oblique ions i

Girija 45
Advance generation of dry etching
In the parallel plate reactive ion etching system, high energetic ions damage
wafer. it is serious issue in ULSI device.

Thus Electron Cyclotron Resonance Plasma Etcher (ECR), Inductively Coupled

and Helicon Wave RF Plasma Etcher are developed.

Girija 46
Typical electron cyclotron resonance
ECR system, microwave energy creates plasma and plasma density increased
by magnetic field.
Electrons rotates in circular path with a particular frequency called “Cyclotron
frequency” at a resonance frequency.
A large numbers of electrons move away to the low magnetic field and also
generate low energetic ions and these ions strike the wafer.
The striking velocity is further minimized by wafer biasing voltage to further
reduce wafer damage.
ECR is most suitable for ULSI, but ECR system is complex and costly.

Magnetic
Magnetic coil Wafer

Water cooling out

coil
Helium coolant out
Microwave window
RF Source
ma

Microwave
Plas

DC Source
Microwave wave guide
Gas Helium coolant in
output
Water cooling in

Magnetic coil
Girija
Gas input 47
Typical inductive couple plasma reactor and helicon
wave RF plasma etching
In both techniques, the wafer is decoupled from plasma source, so that only
low energetic ions are allowed to strike the wafer.
Used for deep submicron etching.
Inductive coupled plasma etcher is produced by RF current through an
induction coil located outside of plasma chamber and electrons path is I
ncreased by magnetic field.
To attract ions wafer is AC biased, which is several skin depths away from the
coil to avoid the loss of plasma density and electromagnetic effect.
Inductive supply Gas inlet
Inductive coil

Tunable Magnet
Dielectric plate
capacitors
Multipole
Loop
magnets RF
Antennas

Wafer

A C Bias wafer holder To reactor

Girija 48