Introduction to

Wave pipelined circuits

Presented by
G. Seetharaman
Outline
Introduction
Wave-pipelining
BIST based Wave-pipelined circuit
SOC based Wave-pipelined circuit
Application
Introduction
 Single stage system
R R a0 1
3
E Comb E 2
G i- G b1 1
3
I nation I 2 1
3
S al S

OUTPUT REGISTER
2

T logic T a1 1

INPUT REGISTER
circuit 3
E E 2

R R b0
clk

a1 1
3
Synchronous non-pipelined circuit b1
2

Dmax = 3 gate delay

Dmin = 2 gate delay

Temporal/spatial diagram of data flow

through the combinational logic circuit.
 Pipelining
R R R
E Combi E Combi E
G - G - G Pipelined circuit
I nation I nationa I
S al S l logic S
T logic T block T
block a0 1
E E E 3
2
R R R b1 1
3
2 1
3

OUTPUT REGISTER
2

a1 1

INPUT REGISTER
3
2
b0
clk
1
a1 3
2

The minimum sampling interval b1

Register
Ts = M + 2.Cnp + tsh + tRF

where M is the worst case combinational block delay

2.Cnp is the worst case clock skew existing entire ckt
tsh setup/hold time and
tRF Rise/Fall time at the CLBlock
Advantages and Disadvantages of Pipelining

Advantages

Higher Speed
Low power

Disadvantages

Area is increased
Latency of the system is increased
The complexity of the clock distribution circuitry is
increased

Latency is defined as the difference b/n the time an o/p is generated and the time at
which its corresponding i/p was received by the system .
Parallel processing
Parallel processing increases the sampling rate by replicating hardware so that
several inputs can be processed in parallel and several outputs can be produced at
the same time. So, in this structure, the SISO (single-input single-output) system is
converted into a MIMO (multi-input multi-output) system.

In a parallel system Tsample  Tclk

whereas in a pipelined system Tsample = Tclk

Two parallel FIR FILTER

Wave-pipelining
Wave-Pipelining
WP is a technique, which can be used to increase the speed of the circuit
without the insertion of registers.
Instead it utilizes the fact that, if the logic path is long enough and the
data dispersion can be reasonably small, multiple sets of data can be sent
through the logic at a faster clock rate without latching the data on the
way.

The rate at which logic can propagate through the circuit depends not on
the longest path delay but on the difference between the longest and the
shortest path delays.

TCK > (DMAX – DMIN) + TS + TH + 2CK

 Wave pipelining advantages and disadvantages

Advantages
The speed of the combinational circuit is increased without
increasing its latency.
No storage element is required other than I/O registers
Lower area
The clock routing complexity and clock skew are minimized
Wide applicability to all pipelined digital circuits

Disadvantages

At each node and at output register, equalization is required

between longest and shortest paths
 Timing constraints for wave-pipelining
By adjusting the latching instant at the output register to lie in the stable
period, the wave pipelined circuit can be made to work properly.

Temporal/spatial diagram of data flow through the combinational logic circuit.

For large logic depths, there may not be any stable period. For such
cases, the clock period has to be increased to increase the stable period.
 Block diagram of wave-pipelined circuit

Three tasks required for maximizing the speed of wave pipelined circuit

Equalization of path delays,

Adjustment of the clock period &
Clock skew

Inequality in path delay can be minimized through UCF

Solutions proposed

Semi-automation procedure (BIST Approach)

Automation procedure (SOC Approach)

Applicable for Xilinx FPGAs

and
Altera FPGAs

Various schemes are tested with both Xilinx and Altera FPGAs
BIST based Wave-pipelined circuit
BIST based Wave-pipelined circuit
FSM (Finite State Machine)

The FSM block generates the control signal to choose between the normal mode
and the self test mode and this is applied to the select input of multiplexer.

In the self test mode, the FSM gradually increases the clock frequency and clock
skew.

For each set, it applies the test inputs and reads the signature analyzer-comparator
outputs.

Repeat the above procedure until it matches with the expected signature output,
and progresses with the testing till the frequency at which the multiplier works for
at least 3 or more consecutive skew values is found.

The operating skew value is chosen to be the middle value so that the multiplier
would reliably work even if the delays change due to environmental conditions.
 Signature analyzer
The signature analyzer consists of
a Pseudo Random Binary
Sequence (PRBS) generator and
signature comparator.

PRBS is constructed from a linear

feedback shift register, which in
turn made of flip-flops connected
in a serial fashion

Test vector generation

In principle, the number of test

vectors required for an M input
combinational logic circuit is 2 M.
If the value of M is small,
exhaustive testing of the circuit
may be carried out
 CLOCK GENERATION
System clock frequency 25 MHz is available.
Spartan II kit
SCHEMES:
Using System clock and DLL
The proposed scheme
Disadvantage :
Clock period cannot be altered during the execution of the program.
proposed scheme
Advantage :
Clock period can be altered
during the execution of the program.
Disadvantage :
Generated clock period depends
on LUT and interconnect delays.
Macro
To retain the position of interconnects and LEs

Methods:
HDL – Simplest
Manual (FPGA editor) – Tedious & Time consuming

Options for placing : Two

Advantage: Simple procedure

Disadvantage: Manual (design & macro) placing
SOC based Wave-pipelined circuit
SOC based wave-pipelined circuit.
 Proposed CLOCK GENERATION scheme
System clock frequency 50, 33.33
MHz is available.

Apex 20K200EFC484,
Cyclone-II EP2C35F672C6

Logic Lock

- To retain the position of

interconnects and LEs

Methods:
HDL – Simplest
Manual (Floor planner)–Time
consuming

Options for placing : Three

Applications
Dedicated AND Gate &XOR array
multiplier