Low-Frequency Harmonic

Reduction in Single-Phase
Power Supply Systems
Javier Sebastián

Universidad de Oviedo
Spain

CIEP’98-1
 Focusing the presentation

Line
{
•Single-Phase

•Three-Phase
Converter
{ •Ac-to-dc
•Ac-to-ac

Power
{ •High power
•Low power
Energy
{ •Recovery to line
•No recovery
(110-220V, <16A)

Philosophy
{ •Modifying conv. topology
•External connection
CIEP’98-2
 Power Factor (PF) and Total
Harmonic Distortion (THD)

Input power
PF=
Input voltage, rms X Input current, rms

(Input current, rms)2 - ( Its 1ST harmonic, rms)2

THD=
Its 1ST harmonic, rms

CIEP’98-3
 Questions (Q) & Answers (A):
•Q: Actually, are PF and THD the most important
parameter from the point of view of regulations?
•A: No, they are not
•Q: What do regulations say about PF and THD?
•A: Almost NOTHING. They only speak about the
maximum value of each harmonic
•Q: Frequently, what is the most usual objective
designing?
•A: To comply with regulations at as a low cost as
possible. Neither PF=1 nor THD=0 are the main
objectives

CIEP’98-4
 Suggestion: to change words
and concepts
Power Factor Correction

Low-Frequency Harmonic Reduction

Objectives: •To comply with regulations

•Low efficiency penalty
•Low cost penalty
CIEP’98-5
 Balanced
3Φ equipment?
Yes Class
A IEC 1000-3-2
No

Portable Class
tool? Yes B

No
igpeak
Lighting Class
equipment? C 35%
Yes

No π/3 π/3 π/3

Clase D Template
Especial
Waveform & Motor driven, Class
P<600 W? D
Yes α control? No

No Yes
CIEP’98-6
Special wave shape for Class D
equipement
igpeak “Each half cycle of
input current is within
the envelope for at
35% least 95% of the time;
peak of current
coincides with center
π/3 π/3 π/3
line”

CIEP’98-7
IEC 1000-3-2: Harmonics limits
n Class A Class B Class C Class D
(A rms) (A rms) (% fun.) (mA/W)
3 2.3 3.45 30PF 3.4
5 1.14 1.71 10 1.9
7 0.77 1.155 7 1.0
9 0.40 0.60 5 0.5

2 1.08 1.62 2 -
4 0.43 0.645 - -
6 0.30 0.45 - -
8<n<40
1.84/n 2.76/n - -
CIEP’98-8
 Type of solutions
Input current waveform
sinusoidal non-sinusoidal

passive & passive &

passive sinusoidal non-sinusoidal

Devices
active & active &
active
sinusoidal non-sinusoidal

CIEP’98-9
 Passive solutions Active solutions

�Robust & reliable �Preregulation

�Cost effective �Small size & low weight
�Low power �No start-up problems
�No preregulation
�Either low & high power
�High weight & big size
�High quality of input
�Start-up problems
current *
�current
Medium quality of input
* � More expensive
� Less robust & reliable

* It depends on the input current goal

CIEP’98-10
Sinusoidal input Non-sinusoidal
current input current
�Ideal operation �Higher efficiency
�Universal compliance �Cheaper
�High power �Either passive or
�Expensive active
�Useless
passive
at 50-60Hz if �Compliance
depending on regul.
�Lower efficiency �Low power
CIEP’98-11
 Type of solutions
Input current waveform
sinusoidal non-sinusoidal

passive & passive &

passive sinusoidal non-sinusoidal

Devices
active & active &
active sinusoidal non-sinusoidal

CIEP’98-12
 Series-resonant tank

�High PF, low THD Useful at HF

�Very bulky elements at (e.g. 20 kHz)
50-60Hz

Voltage
IB
Current
Either
CR
dc-to-ac
LR or dc-to-dc
CB
VB converter

CIEP’98-13
 Design trade-off
Voltage Q= Z/R
Z=(LR/CR)1/2
R=VB/IB
Current
Low Q The higher Q is:
�The higher PF is
Voltage �The lower THD is
�The higher stresses
Current in devices are
�The bulkier the
inductor is
High Q
CIEP’98-14
 Type of solutions
Input current waveform
sinusoidal non-sinusoidal

passive & passive &

passive sinusoidal non-sinusoidal

Devices
active & active &
active sinusoidal non-sinusoidal

CIEP’98-15
 LC input filter with dc-side
inductor (I)
•Up to 300W
•Design in Class D
Voltage •Different results if ac-side
inductor
Current

Either
LF dc-to-ac
or dc-to-dc
CB converter

CIEP’98-16
 LC input filter with dc-side
inductor (II)
200W, 180-260V
igpeak
23.3mH, EI-62.5,
0.58lb, 1.1W (losses)
35%

200W, 90-260V
π/3 π/3 π/3
Class D template 23.3mH, EI-87, 1.57lb,
2.74W (losses)

Current CIEP’98-17
 LCC input filter with dc-side
inductor & capacitor (I)

Voltage •Up to 300W

•Design in Class A
•Different results if ac-side
Current inductor LF & CF

Either
CF LF dc-to-ac
or dc-to-dc
CB converter

CIEP’98-18
 LCC input filter with dc-side
inductor & capacitor (II)
Designing for Class A operation
igpeak
Class D
template
35%

π/3 π/3 π/3

Class D template

CIEP’98-19
 Type of solutions
Input current waveform
sinusoidal non-sinusoidal

passive & passive &

passive sinusoidal non-sinusoidal

Devices
active & active &
active non-sinusoidal
sinusoidal

CIEP’98-20
 Resistor Emulator concept
vg(ωt) VO
ig(ωt) IO
iO(ωt)
iO(ωt) IO
ig(ωt) Resistor
Emulator
vg(ωt) (dc-to-dc VO
converter)

pg(ωt) pO(ωt)
PO
PO CIEP’98-21
Resistor Emulator’s properties (I)

VO VO/ Vg
m(ωt)= = VO ≈const.
vg(ωt) vg(ωt) ⎜sin(ωt)⎜

Resistor
Emulator
vg(ωt) (dc-to-dc VO
converter)

•The voltage conversion ratio m(ωt)

changes from VO/ Vg to infinity
CIEP’98-22
PO
Resistor Emulator’s properties (II)
VO
VO R IO
r(ωt)= = iO(ωt)
iO(ωt) 2sin2(ωt)
iO(ωt) IO
Resistor
Emulator VO
(dc-to-dc
converter)
R=VO/IO

•The load resistance seen by the converter,

r(ωt), changes from R/2 to infinity
CIEP’98-23
PO
Consequences of these properties
(examples) (I)
ig
VO From
vg property #1

Buck working
vg

Buck off VO

⎜ig ⎜

A Buck conv. cannot work as resistor emulator

CIEP’98-24
Consequences of these properties
(examples) (II)

•Series Resonant Converter (SRC) cannot be

used as Resistor Emulator (from property #1)
•Zero-Voltage-Switched Quasi Resonant
Converters (ZVS QRC) cannot be used as
Resistor Emulator (from property #2), because
they cannot operate at no load.

CIEP’98-25
 Consequences of these properties
(examples) (III):
Study of the current conduction mode (I)

L L
R
Vg Standard
dc-to-dc VO Resistor
Emulator r(ωt) R VO
vg(ωt)
M=VO/Vg
m(ωt)=VO/vg(ωt)
K(R)=2L/(RT)
k[r(ωt)]=2L/[r(ωt)T]
K(R)>Kcrit(M) CCM
K(R)<Kcrit(M) DCM k[r(ωt)]>kcrit[m(ωt)] CCM
k[r(ωt)]<kcrit[m(ωt)] DCM
Dc-to-dc Ac-to-dc
CIEP’98-26
Consequences of these properties
(examples) (IV):
Study of the current conduction mode (II)

k[r(ωt)]>kcrit[m(ωt)] CCM
k[r(ωt)]<kcrit[m(ωt)] DCM

k’crit[m(ωt)]= kcrit[m(ωt)]/[2sin2(ωt)]
Kapparent(R)=2L/(RT)

Kapparent(R) >k’crit[m(ωt)] CCM

Kapparent(R) <k’crit[m(ωt)] DCM
CIEP’98-27
Consequences of these properties
(examples) (V):
Study of the current conduction mode (III)

Kapparent(R) >k’crit[m(ωt)] CCM

Kapparent(R) <k’crit[m(ωt)] DCM

max. of {k’crit[m(ωt)]} = k’crit max

min. of {k’crit[m(ωt)]} = k’crit min

ALWAYS CCM Kapparent(R) > k’crit max

ALWAYS DCM Kapparent(R) < k’crit min
CIEP’98-28
Consequences of these properties
(examples) (VI):
Study of the current conduction mode (IV)

ALWAYS CCM Kapparent(R) > k’crit max

ALWAYS DCM Kapparent(R) < k’crit min

vg(ωt)= Vg PEAK sin(ωt) M=VO/Vg PEAK

K’crit max K’crit min

Buck-Boost, 1/(2M2) 1/(2M+1)2
SEPIC, Cuk
Boost 1/(2M2) (M-1)/(2M3)

CIEP’98-29
Control of Resistor Emulators (I)
Multiplier approach control (I)

dc-to-dc
converter

Input current fixed by the reference

CIEP’98-30
Control of Resistor Emulators (I)
Multiplier approach control (II)

dc-to-dc
converter

Input current sinusoidal & its

value fixed by the reference
CIEP’98-31
 Control of Resistor Emulators (I)
Multiplier approach control (III)
dc-to-dc
converter

Low-pass
filter

Input current sinusoidal & its value fixed by

the voltage feedback loop CIEP’98-32
Control of Resistor Emulators (II)
Voltage-follower approach control

dc-to-dc
converter

Filter Bulk
Controller for
dc-to-dc conv.

Low-pass
filter

CIEP’98-33
 Control of Resistor Emulators (III)
Multiplier vs. Voltage-Follower
Multiplier Voltage-Follower

�Either low or high output-

impedance topologies
�Perfect PF & THD
�Lower losses in the
transistor
�Current sensor
�Multiplier
�More expensive
�No current sensor
�No multiplier
�Cheaper
�Lower losses in the diode
�Only high output-
impedance topologies
�Sometimes THD
CIEP’98-34
Control of Resistor Emulators (IV)
Improving THD in some converters with
voltage-follower control

dc-to-dc
converter

New
block
Low-pass
filter
CIEP’98-35
Resistor emulator topologies (I)
One switch, no isolation (I)

Boost

Buck-boost
CIEP’98-36
Resistor emulator topologies (II)
One switch, no isolation (II)

SEPIC

Cuk
CIEP’98-37
 Resistor emulator topologies (III)
Comparing basic topologies

stress in inductor at switch to VO/ Vg galv. Protection

semic. the input GND isolation
(possibl.)
Boost Low Yes Yes >1 No No

Buck- High No No <1, >1 Yes Yes

Boost
SEPIC & High Yes Yes <1, >1 Yes Yes
Cuk

CIEP’98-38
 Resistor emulator topologies (IV)
•One switch
•Isolation

Flyback

SEPIC

Cuk CIEP’98-39
 Resistor emulator topologies (V)
Voltage-Follower control (I)
Buck-Boost
ig av iL in DCM
iS

ig av
iL

iS ig av

Ideal Resistor
Emulator CIEP’98-40
 Resistor emulator topologies (VI)
Voltage-Follower control (II)

ig av Boost in DCM,
fS=const.
iL

iL ig av
ig av

Non-ideal Resistor
Emulator
CIEP’98-41
 Resistor emulator topologies (VII)
Voltage-Follower control (III)
Boost in the
ig av boundary
iL DCM/CCM

ig av
ig av iL

ton toff

•ton const. each cycle Ideal Resistor

•toff depends on vg=(ωt)
•Therefore, fS=variable
Emulator
CIEP’98-42
 Resistor emulator topologies (VIII)
Voltage-Follower control (IV)
iL
ig av SEPIC & Cuk
in DCM

ig av
iL ig av

Ideal Resistor Emulator

(very low input current ripple)
CIEP’98-43
 Resistor emulator topologies (IX)
Two switches, no isolation

Vg VO
Buck Boost

Boost=off Vg
Buck=swt.
Boost=swt.
VO
Buck=on

CIEP’98-44
Resistor emulator topologies (X)
Two switches, isolation

To avoid starting-up &

stopping problems

Current-Fed Push-Pull
CIEP’98-45
 Resistor emulator topologies (XI)
High-frequency topologies (I)

Resonant
�Integration of parasitics
�Only one switch
�Either ZCS or ZVS
�High output impedance (voltage- �Constant frequency
follower control)
�Higher stress (conduction
losses)
�Frequency modulation
Soft-switching
PWM
�Stress similar to PWM
�Either ZCS or ZVS
� Several switches
� Complex controller

CIEP’98-46
 Resistor emulator topologies (XII)
High-frequency topologies (II): parasitic
integration
LR
CR CB
ZCS-QR
SEPIC

C’R
LR
CB

Transformer
Diode
CIEP’98-47
 Resistor emulator topologies (XIII)
High-frequency topologies (III): parasitic
integration

PRC

C’R

LR
Transformer
Diodes
Switches
CIEP’98-48
 Resistor emulator topologies (XIV)
High-frequency topologies (IV):
voltage-follower control in resonant converters

Voltage Voltage

Current
Current

ZCS-QR SEPIC PRC

CIEP’98-49
Resistor emulator topologies (XV)
High-frequency topologies (V): Zero Voltage
Transition topologies
Main diode
CD

LR
CS CR

CB

Main switch Aux. devices

ZVT Boost
CIEP’98-50
Resistor emulator topologies (XVI)
High-frequency topologies (VI): Zero Voltage
Transition in IGBT using a MOSFET

Saux CB
S1 S2
S1
Main S2
switches Saux
Aux. switch
Current-fed Push-Pull
CIEP’98-51
 Dynamic problems in Resistor
Emulators
With multiplier approach control

dc-to-dc
converter

High gain at
100-120Hz
sin
10dB lower
20dB lower
Low-pass
filter
Input current
Same case with for different filters
Voltage-Follower CIEP’98-52
 PFC based on an one-stage
Resistor Emulator
voltage voltage

�Cheap
Resis. �Efficient
Emul.
power
�Poor dynamics
power
LOSSES �Big bulk
capacitor

CIEP’98-53
 Fast-response topologies
•Two stages in cascade
•Topologies with double
power-processing •Two-stage integrated
topologies

•Topologies with power •“Charge Pump” or “Line-

processing lower than Voltage Augmentation”
double type

•Parallel PFC’s

•Based on High-Efficient
Post-Regulators
CIEP’98-54
 Two-stage PFC (I)

voltage voltage
voltage
�Good dynamics
�Smaller bulk
capacitor*
Resis.
Emul. 2nd S.
�Lower efficiency*
power
LOSSES LOSSES
�Expensive

* In comparison with one-stage Resistor Emulators

CIEP’98-55
 Two-stage PFC (II)
Example

Resistor Emulator
(Boost)
Dc-to-dc converter (Phase-
Shifted Full Bridge)

CIEP’98-56
Two-stage integrated topologies (I)

voltage
�Good dynamics
voltage voltage � Smaller bulk
capacitor

�Cheaper
Fast-PFC
Fast-PFC �High stress
power
�Low efficiency
LOSSES

CIEP’98-57
 Two-stage integrated topologies (II)

Dc-to-dc converter
Resistor Emulator (Either DCM or CCM
(DCM Boost) Flyback)

CIEP’98-58
 Two-stage integrated topologies (III)

ig av

•DCM Boost + Flyback

•If Flyback in DCM, lower
voltage variation across CB
ig av •Quasi-sinusoidal input current

� High voltage & current

stress in the transistor

CIEP’98-59
 Two-stage integrated topologies (IV)

ig av

ig av •DCM SEPIC + Flyback

•If Flyback in DCM, lower voltage variation
across CB (even no variation)
•Sinusoidal input current

�High current stress in the transistor

CIEP’98-60
Two-stage integrated topologies (V)
Boost Integrated with Flyback Rectifier/Energy
storage/Dc-to-dc converter (BIFRED)

ig av

ig av
•Almost the same as
DCM Boost + Flyback

CIEP’98-61
Two-stage integrated topologies (VI)
Integrated Resistor Emulator + inverter
ig av

ig av
Fluorescent
Lamp

•DCM Boost Resistor Emulator + Half-Bridge

Parallel Resonant inverter
CIEP’98-62
 “Charge Pump” or “Line-Voltage
Augmentation” type topologies (I)
voltage voltage

�Good dynamics
�Small bulk capacitor
voltage �Higher efficiency
�Complex
Fast-PFC � Double control
(for perfect input
power current)
voltage
LOSSES

CIEP’98-63
 “Charge Pump” type topologies (II)

pg(ωt) vS(ωt)
pS(ωt) pS(ωt) ⎥ ig(ωt) ⎜

VS(ωt)
⎥ ig(ωt) ⎜
ig(ωt) dc-to-dc
vS(ωt) or
pg(ωt) dc-to-ac
⎥ vg(ωt) ⎜ VB converter

⎥ vg(ωt) ⎜
VB
⎥ ig(ωt) ⎜ vS(ωt) pS(ωt)=0.27pg(ωt)

CIEP’98-64
 “Charge Pump” type topologies (III)
Example:double Forward-Flyback

vS(ωt) pg(ωt)
⎥ ig(ωt) ⎜ pS(ωt)
⎥ ig(ωt) ⎜
pS(ωt)>0.27pg(ωt)
vS(ωt)

VB

•vS(ωt) operates in DCM

•vS(ωt) controlled by FM
CIEP’98-65
 “Charge Pump” type topologies (IV)
Example:Full-Bridge + FM PRC
vS(ωt) pg(ωt)
⎥ ig(ωt) ⎜ pS(ωt)
pS(ωt)>0.27pg(ωt)
vS(ωt)
- +

VB/2

VB/2

FM PRC Full Bridge

CIEP’98-66
 Parallel PFC (PPFC) (I)

Power undergoing 2
Input power transformations (32%)
Output
power

Power undergoing only

1 transformation (68%)
CIEP’98-67
 Parallel PFC (PPFC) (II)
power
power
�Good efficiency
�Several S aux

2nd stg.
�High stress S aux

Main stg.
� Difficult design
and control
power LOSSES
68%
power

CIEP’98-68
PPFC (III): Example

CB
Forward

Current-fed Full Bridge

CIEP’98-69
High-Efficient Post-Regulators Concept
1.15·VBus - 0.87·VBus
VBus
Line High-Efficient Post-
One-stage Regulator
PFC η > 95%

PFC No galvanic
CONTROLLER isolation -
PWM
+
LOW-PASS -
FILTER +

•Two-Output One-stage PFC + Two-Input Buck (TIBuck)

•Standard One-Stage PFC + Series-Switching Post-
Regulator (SSPR)
CIEP’98-70
 High-Efficient Post-Regulators (I)
Two-Output Resistor Emulator + Two-
Input Buck (TIBuck)

Line Two-output V1 Bus

Resistor
Emulator V2 TIBuck

PFC PWM -
CONTROLLER +

LOW-PASS - POST-REGULATOR
FILTER +

CIEP’98-71
High-Efficient Post-Reg. (II): TIBuck
V1-V2 VO
VO
V1
V2
V2

V1-V2 VO-V2
V1-V2

VO-V2
V2 V2 V2 V2

V2IO undergoing no power processing, (VO-

V2)IO undergoing power processing CIEP’98-72
 Computing TIBuck’s efficiency
η HB is Buck Half-
ηHB
η TB = -Converter
V2 efficiency
1 −(1 −η HB )
VO η TB is TIBuck
efficiency
TIBUCK EFFICIENCY
100
90%
85%
80 75%
η HB=50%
60

0.4 0.6 0.8 1

V2/VO CIEP’98-73
 High-Efficient Post-Regulators (III)
Power processing in a PFC based on a TIBuck

power voltages
V1 PO power
P1 VO
V2 PO2
PO1
P2

P1 V1 PO1 VO
R.Em. TIBuck PO
P2 V2 85-90% PO2

LOSSES
ηTB=99-97% LOSSES

CIEP’98-74
High-Efficient Post-Regulators (IV)
Example: Two-output Flyback + TIBuck

V1=62V VO=54V

V2=47V -
PWM
R. Em. +

PFC
CONTROLLER
LOW-PASS
FILTER
-
+
TIBuck

η=85-82%, vg=85-264V rms

CIEP’98-75
 High-Efficient Post-Regulators (V)
Series-Switching Post-Regulator (I)

VOC
- +
One-stage + +
PFC (Resistor Isolated dc-
VO to-dc VOSS
Emulator) converter
- -
-
PFC PWM +
CONTROLLER

LOW-PASS -
SSPR (non-isolated )
FILTER +
VOC<< VO
Pconv.<<PPFC
CIEP’98-76
 Computing SSPR efficiency (I)
IO IO2 VOC IO2
- +
+ IO1 Dc-to-dc +
VO converter VOSS
- ηC
-
SSPR -
ηss PWM +

VOSS= VO+ VOC SSPR efficiency:

IO= IO1+ IO2 VOSS·IO21+KO
ηSS= =
VOC·IO2 VO·IO KO
ηC = 1+ η
VO·IO1 KO=VOC/VO C
CIEP’98-77
Computing SSPR efficiency (II)
ηSS [%]
100 Transient
response
95 0.1
vOSS
0.2
vOC
90
KO=0.3 Voltages Steady state
85
KO=VOC/VO
ALWAYS
vO
80 VOSS>VO
60 70 80 90 100
Conv. efficiency, ηc [%] Time

ηC=80%
KO=VOC/VO=0.1 ηss=97.7%
CIEP’98-78
High-Efficient Post-Regulators (VI)
Series-Switching Post-Regulator (II)
Power processing voltage & power

vOSS
voltage vOC vO
vO vOC
DC/DC

R. Em. 85-90%
power
SSPR
LOSSES LOSSES vOSS
ηSSPR=97-98% CIEP’98-79
 High-Efficient Post-Regulators (VII)
Series-Switching Post-Regulator (III)

Same type of
converter Dc-to-dc
converter

Dc-to-dc
One-stage Dc-to-dc converter
PFC converter n convert
Dc-to-dc
SSPR converter

Dynamic response Dc-to-dc

converter
improves by using n+1
converters instead of n
CIEP’98-80
 High-Efficient Post-Regulators (VIII)
Series-Switching Post-Regulator (IV)

VOC=7V
- +
+ *
VO=47V
+
VOSS=54V
- -
*For discharging C B in short-circuit
Implementation based
on a Forward converter
CIEP’98-81
 High-Efficient Post-Regulators (IX)
Setting voltages

TIBuck SSPR
Transient response Transient
v1 response
vOSS
Voltages
vO
Voltages
Steady state v2 Steady state vO
ALWAYS ALWAYS
V1>VO>V2 VOSS>VO
Time Time
A good trade-off:
V2 ≈0.7-0.8V1 A good trade-off:
VO ≈0.7-0.8VOSS
VO ≈ (V1+V2)/2
CIEP’98-82
 Topologies based on TIBuck (I)

Current-Fed
Push-Pull

TIBuck

CIEP’98-83
Topologies based on TIBuck (II)

2xBoost

TIBuck

CIEP’98-84
Topologies based on SSPR

Boost

Forward
SSPR

Flyback

Forward
SSPR

CIEP’98-85
PPFC versus 1 stg. PFC + SSPR

Forward

PPFC

1 stg. PFC + SSPR

Current-fed Full Bridge

Current-fed Full Bridge Forward SSPR

CIEP’98-86
PPFC versus 1 stg. PFC + SSPR

�Smaller capacitor power

power
2nd stg.
power
power Main stg. 68%
power
LOSSES

power
POSS
POC
DC/DC Pd
POSS POC

1-stg.

�Higher %
PFC 85-90%
SSPR

LOSSES Pd LOSSES �Simpler control

CIEP’98-87
 Type of solutions
Input current waveform
sinusoidal non-sinusoidal

passive & passive &

passive sinusoidal non-sinusoidal

Devices
active & active &
active sinusoidal non-sinusoidal

CIEP’98-88
 Example: Buck PFC
One switch, no isolation, slow response

ig
VO
vg Always:
VO<Vg peak
Buck working vg
Buck off VO �No start-up problems
�Low stress in devices
vg vg �response
Slow transient
ig ig

CIEP’98-89
 Objectives for many new
converters

Small size ⇒ Reactive elements at switching frequency

Cheap ⇒ Only one transistor & controller

Efficient ⇒ Less than two power conversions

Always complying with the regulations (IEC 1000-3-2)

PF=1 & THD=0 is not the main worry!

CIEP’98-90
 “Line-voltage augmentation” based
on an additional output in dcm
Additional output in dcm
To help input
rectifier to start
conducting

Line
Load
Conventional dc-
vLine to-dc converter
Bulk
iLine cap.

CIEP’98-91
 Additional output in
dcm

vLine

iLine Example I
Bulk cap.

Filter cap.
Line
Flyback

vLine

iLine
Line
Bulk cap. Load
Filter cap.
INTELEC’96
CIEP’98-92
 Example II

Additional output in dcm

vLine

iLine

Line

INTELEC’96 2 Switch Forward

CIEP’98-93
 Example III
DCM
Flyback

CB

Forward with additional DCM

Flyback-type output
CIEP’98-94
Characteristic
vO(is) Equivalent circuit with
additional output in dcm
is Non-linear
- vO(is) + Loss-Free Resistor
vLine

iLine
is dc-to-dc
standard
Bulk
Line cap. converter Load

�Much energy re-cycled

�High current stress (dcm)
�Large variation in cap’s voltage CIEP’98-95
Characteristic
vO(is) Desired equivalent
circuit
is Linear
- vO(is) + Loss-Free Resistor
vLine is
iLine
dc-to-dc
standard
Bulk
Line cap. converter Load

�Less energy re-cycled

�Lower current stress (ccm)
�Smaller variation in cap’s voltage CIEP’98-96
 How can it be implemented?
Forward with LD and with L in ccm
iLD iL iO Driver
D1

LD L
D2 VO Voltage across D2
Vi
1:1 : n
iL iO
Characteristic
iLD

{
VO=n·Vi·d - LD·fS·iO vO(iO)
O
{
V =V - R ·i
S LF O
VS

iO
td
t=d/fS
1/fS
VS/RLF
CIEP’98-97
 Forward with LD &
with L in ccm
vLine Circuit
L LD
iLine proposed
Line
this year
Bulk cap. (APEC’98)
Filter cap.
Flyback

vLine
L
iLine
LD
Load
Line Bulk
cap.
CIEP’98-98
 Active Input-Current Shaper (AICS)
VO(0)=VS
is vO(is) n1 With extra
nS
n2 tap

VS can be freely
AICS chosen

vO(is)
Without
n1 n2 extra tap

AICS VS depends on
the duty cycle
CIEP’98-99
Generalization of the AICS concept

AICS

Forward converter
(conventional)

AICS

Forward converter
with active clamp
CIEP’98-100
 Designing the Active Input-
Current Shaper
VS(Vg,PO) RLF

vg=Vgsinωt
dc-to-dc P
vLine VC(Vg,PO) converter O
iLine
φC

Vg min VS min(Vg min , PO max) VC(Vg,PO)

Vg max RLF to minimize
φC(Vg,PO)
PO max re-cycled energy

CIEP’98-101
 Determining “Class” and
compliance (IEC 1000-3-2)

Special wave shape

2.5% 2.5%
Class A: φC>86.3º
compl. up to high
power levels (≈1kW)

Class D: φC<86.3º
φC=86.3º compl. if φC>67.4º
Boundary between
Class A & Class D
CIEP’98-102
 VS min= Vg min
Design example 1 d max=0.66
Vg max=1.2· Vg min

1
Input current
180º
φ C 3
VC/Vg
Vgmin,
Pmax Vgmin
Vgmax,
Pmax
Class A
120º 2
0.5 Vgmax Vgmax
Vgmax,
Pmax/2 boundary
60º 1 Vgmin
Class D
0 Vgmin, Pmax/2
0º 0
0 π/3 2π/3 π 0 0.5 1 0 0.5 1
Line angle Normalized power Normalized power

�High PF & low THD

�High V variation
C CIEP’98-103
 VS min= Vg min/2
Design example 2 d max=0.66
Vg max=1.4· Vg min
φC VC/Vg
1 Input current 180º 3
Vgmin, Class A
Vgmax, Pmax Vgmin
Pmax/2 120º 2
0.5
Vgmax
boundary
60º Vgmax 1 Vgmin
0
Class D
0º 0
0 π /3 2π/3 π 0 0.5 1 0 0.5 1
Line angle Normalized power Normalized power

�Lower V variationC

�Lower PF & higher THD CIEP’98-104

 Experimental results: prototype

Without extra tap

1.4mH

Line
430μH

VC
Output
Bulk
cap.
Vg=190V-250V
VO=50V, IO=0.5-2A
fS=100kHz

CIEP’98-105
 Efficiency in the prototype
94

270 V dc As dc-to-dc converter

fficiency92
[%] 355 V dc
(voltage source across
the bulk capacitor)
310 V dc
90
25 50 75 100
Output Power [Watts]

190 V rms
88
As ac-to-dc converter
fficiency [%]
250 V rms with Input-Current
84
220 V rms Wave-Shaping.
η = 3-7 points lower
80
25 50 75 100
Output Power [Watts]

CIEP’98-106
 Input current waveforms &
harmonics

Current 0.5
0.87 A/div
0.4 Pinput=121 W
ENVELOPE PF =0.845
0.3 THD=52%
PO=100W Input current [A]
0.2 IEC 1000-3-2
Measured
0.1

Current 0
0.43 A/div 2 3 4 5 6 7 8 9 10 11 12 13 14
nth Harmonic
ENVELOPE

PO=50W

CIEP’98-107
 Input current
(transformer with extra tap)

voltage voltage
(50V/div) (100V/div)
current
current (0.67AV/div)
(0.67AV/div)
envelope Class D
Class A

110V, 100W 220V, 100W

CIEP’98-108
 AICS: Conclusions
•Main conventional topologies (no extra switches)
•Only 2 additional inductors and 2 additional diodes
•High-frequency filtered input current (ccm)
•Low “extra” stress (ccm & low capacitor voltage
change)
•Main converter either in ccm or dcm
•Trade-off between harmonics and re-cycled energy
(efficiency)
•Compliance with IEC 1000-3-2 with low efficiency
penalty

CIEP’98-109
 Other types of “shapers”(I)
(APEC’97)
Either ccm or dcm.
If ccm, leakage inductance is needed

CIEP’98-110
 Other types of “shapers”(II)
(Magnetic switch, INTELEC’95)
dcm

CIEP’98-111
 Conclusions

•Passive, non-sinusoidal solutions are very

interesting for low-power applications.
•Topologies based on Resistor Emulators
need topological transformations in order to
improve dynamic response.
•Active, non-sinusoidal solutions are very
interesting from the point of view of cost.
This is a promising field for researching.

CIEP’98-112