Low Power Design

Prof. A. K. Swain

Book: Gary Yeap, PRACTICAL LOW POWER DIGITAL VLSI DESIGN

 Introduction
• Analog designers are more worried for low power circuit design.
• Now mainstream digital design community are interested into power due to its impact on all
aspects of the design process.
• The interests in low power chips and systems are driven by both business and technical needs.
• The industry for low power consumer electronic products is booming with a rapidly expanding
market.
• At the same time, newer generations of semiconductor processing technologies present more
stringent requirements to the power dissipation of digital chips due to increased device
density, speed and complexity.
• Power is the rate at which energy is delivered or exchanged.
• An analogy of energy and power is water and its flow rate.
• In a VLSI chip, electrical energy is converted to heat energy during operations.
• The rate at which energy is taken from the source and converted into heat is the power
dissipation.
• Heat energy has to be dissipated from the chip to avoid an increase in chip temperature,
which can cause temporary or permanent circuit failure.
 Introduction
• A decision onlow power technique  involves tradeoffs from different sources pulling in various
directions.
• Major criteria the impact to the circuit delay
(which affects the performance and throughput of the chip)
the chip area
(which directly translates to manufacturing costs)
 design cycle time, testability, quality, reliability, reusability, risk, etc.,
• Task of a design engineer is to carefully weigh each design choice within the specification
constraints.
• The basic understanding of the fundamental circuit theory of power dissipation is imminent
 Needs for Low Power VLSI Chips
Higher device density:
 device density and operating frequency were low.
 Improvement in the scale of integration improves integrates more transistors, faster and smaller
than their predecessors into a chip
 Steady growth of the operating frequency and processing capacity per chip
 Resulting in increased power dissipation.
Demand for portable consumer electronics powered by batteries:
 Smaller, lighter and more durable electronic products indirectly demands low power
requirements.
 Battery life is deciding the fate of a product in electronic markets.
 Being the heaviest and biggest component in many portable systems, batteries have not
experienced the similar rapid density growth compared to electronic circuits.
 Needs for Low Power VLSI Chips

Low power chips and systems from environmental concerns.

 Modem offices are now furnished with office automation equipment that consume large amount
of power.
 A study by American Council for an Energy-Efficient Economy estimated that office equipment
account for 5% of total US commercial energy usage in 1993 and could rise to 10% by the year
2000 if no actions are taken to prevent the trend [1.3].
 Computers are the fastest-growing electricity loads in the commercial sector.
 Since electricity generation is a major source of air pollution, inefficient energy usage in
computing equipment indirectly contributes to environmental pollution.
 The problem has prompted The US Environmental Protection Agency and The US Department of
Energy to promote the Energy Star program [1.4] that sets guidelines for the energy usage of
computing equipment.
 Needs for Low Power VLSI Chips
High performance computing system:
 Characterized by large power dissipation that drives the low power needs.
 The power dissipation of high performance microprocessors is now comparable to that of a hand-
held soldering iron.
 Power dissipation has a direct impact on the packaging cost of the chip and the cooling cost of
the system.
 A chip that operates at 3.3V consuming 10W means that the average current is 3A.
 The transient current could be several times larger than the average current.
 This creates problems in the design of power supply rails and poses big challenges in the analysis
of digital noise immunity.
 Charging and Discharging Capacitance
Fundamental physical mechanisms, its equation of power dissipation in digital CMOS VLSI circuits.

Power dissipation in CMOS circuits:- static and dynamic.

Static power dissipation is related to the logical states of the circuits rather than switching activities.
In CMOS logic, leakage current is the only source of static power dissipation.
However, Such parasitic capacitance cannot be avoided and it has a significant impact on the power dissipation of
the circuits.

Dynamic power dissipation is caused by switching activities of the circuits.

A higher operating frequency leads to more frequent switching activities in the circuits and results in
increased power dissipation.
Dynamic power dissipation in CMOS circuits is due to the charging and discharging of capacitance.
Most digital CMOS circuits do not require capacitors for their intended operations. The capacitance forms due
to parasitic effects of interconnection wires and transistors.
The estimation and analysis of parasitic capacitance is a crucial subject matter not only for signal delay, but
also for power.
 Charging and Discharging Capacitance

Equivalent circuit of charging and discharging output capacitance of a CMOS logic gate.
 A switch that flips up and down to model the charging and discharging cycles.
 V is an ideal constant voltage source
 Rc (Rd ) is the resistance of the charging (discharging) circuitry,
(intentional or parasitic)
Charging and Discharging Capacitance
Charging and Discharging Capacitance
 Charging and Discharging Capacitance

Equation (1.7) is the most important power dissipation equation in digital VLSI chip design.
Observation:
 During charging, energy is drawn from the energy source, half of which is dissipated in the charging
resistance Rc and the other half is stored in the capacitor.
 During discharging, the energy stored in the capacitor is dissipated as heat in the discharging resistor
Rd.
Few assumptions are made in our derivation:
 The capacitance CL is constant, The voltage V is constant.
 The capacitor is fully charged 0v to V and discharged from V to 0V.
 The result is independent of the charging and discharging circuitry Rc, Rd.
 The length of charging and discharging cycle t0,t1 and t2 ;
 The voltage or current waveform Vc(t), Ic(t), etc.
Charging and Discharging Capacitance
 Short-circuit Current of an Inverter
CMOS inverter operating at Vdd,
Threshold voltages of Vtn and Vtp
If input signal >Vtn the N-transistor is turned on.
If input signal < Vtp the P-transistor is turned on.

When the input signal Vi switches

 for short duration (input level is between Vtn and Vtp)
 both transistors are turned =>
Þ Results a short-circuit current from Vdd to ground

• Energy drawn from the source is dissipated as heat in the P and N -transistors.
 Short-circuit Current of an Inverter
The current = zero when the input signal is below Vtn or above Vtp.
The current increases as Vi rises beyond Vtn and decreases as it approaches Vtp.
The integration of the current over time multiplies by the supply voltage is the energy dissipated during
the input transition period.

The shape of the short-circuit current curve is dependent on several factors:

1. The duration and slope of the input signal.
2.The I-V curves of the P and N transistors
(depend on their sizes,
process technology,
temperature, etc.)
3. The output loading capacitance of the inverter.
Power dissipation is generally 10-60% of
the total power dissipation of a CMOS gate
 Short-circuit Current Variation with Output Load
Observation:
 The short-circuit current envelope is the largest when the output capacitance is the smallest.
 As the output capacitance increases, the current envelope becomes smaller and eventually approaches zero.
 However, the duration of the short circuit current is independent of the output capacitance because it depends on
the input signal slope only.

 The short-circuit current is non-zero only

when the input voltage is between Vtn and Vtp.

 Increasing the output loading capacitance has

the effect of reducing the short-circuit energy per transition.
 Total Current Variation

One might question whether increasing the output loading capacitance can reduce power
dissipation of the circuit because of smaller short circuit current.
Keeping all conditions identical and vary only the output capacitance.
The total current, i.e., the sum of short-circuit current and the capacitance charging or discharging
current.
• When the output capacitance is increased, the total current always increases in peak as well as
duration(width).
• This means that increasing the output capacitance decreases the short-circuit power dissipation
but the sum of capacitive and short-circuit power increases.
• Capacitance is always the enemy of power efficiency.
• Low power digital design to reduce loading capacitance.
 Short-circuit Current Variation with Input Signal
Slope
Results:
Input signal slope (longer signal transition time) deteriorates,
=>the short-circuit current peak but the duration increases.

To improve power efficiency of a CMOS circuit, we should

Use the fastest input signal slope for all signals.
Leakage Current
o Leakage current exists as a natural phenomenon of the semiconductor device operation.
o Leakage is a form of current that is generally not intended for the normal operation of a digital
circuit.
o Generally, leakage current serves no useful purposes.
• In circuits that use MOS transistors,
There are two major sources of leakage current:
1. reverse biased PN-junction current and,
2. subthreshold channel conduction current.

The first source of leakage current occurs when the source or drain of an N-transistor is at Vdd
and (P-transistor) is at (Gnd).
• PN-junctions are formed at the source or drain of transistors because of a parasitic effect of the
bulk CMOS device structure.
• As shown in Figure 1.7, the junction current at the source or drain of the transistor is picked up
through the bulk or well contact.
 Reverse Biased PN-junction
• The magnitude of the current depends on the temperature, process, bias voltage and the area of the PN-
junction.
• Analysis of the semiconductor physics shows that the reverse biased PN-junction current is

• The current Is is the reverse saturation current dependent on the fabrication process and the PN-junction
area.
• The variable Vth, which often appears in leakage equations, is called the thermal voltage where
Vth = kT/q (1.12)
• In the above equation, k = 1.38 x 1O-23Joule/K is the Boltzmann's constant,
• q = 1.60 X 1O-19C is the electronic charge and T is the device operating temperature.
• At room temperature, T = 300K and Vth = 25.9mV.
• The reverse saturation current Is is of the order of IpA/um2 for today's process.
 Subthreshold Channel Leakage
The second source of leakage current is the sub-threshold leakage through a MOS device channel.
Even though a transistor is logically turned off, there is a non-zero leakage current through the channel at
the microscopic level, as illustrated in Figure 1.8.
This current is known as the sub-threshold leakage because it occurs when the gate voltage < Vth

Other than the device dimension and fabrication process, the magnitude of the Isub depends on:
gate voltage VgS, drain voltage Vds and temperature.
The dependency on Vds is insignificant when it is much larger the thermal voltage.
Sub-threshold Channel Leakage
Leakage Current in Digital Design
Sub-threshold leakage and reverse-biased junction leakage have very similar characteristic.
 They are both in the order of pico-Ampere per device and
 very sensitive to process variation.
 Both increase dramatically with temperature and are relatively independent of operating voltage
for a given fabrication process.

 Most large scale, high performance digital chips operate in high frequency regions in which the
dynamic power dissipation is several million times larger than the leakage current.
 For small custom circuits, especially analog circuits, in which the designers have full control over
the layout and transistor sizes, leakage current analysis can be performed using SPICE simulation
or simple rule of thumb calculation.
 However, as we move toward next generation CMOS fabrication processes with very low device
threshold and operation voltage, leakage current may become a limiting factor.
 This poses low power challenges for device and process designers.
Basic Principles of Low Power Design
 Study of the basic principles can help the readers to develop a global picture of the low power solution
techniques and inspire new low power ideas.
 It should be emphasized that no single low power technique is applicable to all situations.
 Design constraints should be viewed from all angles within the bounds of the design specification.
 Low power considerations should be applied at all levels of design abstraction and design activities.

Trade-off considerations:
 Chip area and speed are the major but a low power design decision also affects other aspects such as
reliability, design cycle time, reusability, testability and design complexity.
 Early design decisions have higher impact to the final results and therefore,
 power analysis should be initiated early in the design cycle.
 Maintaining a global view of the power consumption is important so that a chosen technique does not
impose restrictions on other parts of the system to offset its benefits.
Reduce Switching Voltage
 The dynamic power of digital chips is generally the largest portion of power dissipation.
 The P = C V2f equation consists of three terms: voltage, capacitance and frequency.
 Due to the quadratic effect of the voltage term reducing the switching voltage can achieve
dramatic savings.
 The easiest method to achieve this is to reduce the operating voltage of the CMOS circuit.
 Other methods seek to reduce voltage swing by using well-known circuit techniques such as
charge sharing, transistor threshold voltage, etc.

Trade-offs to be considered in voltage reduction:

 Performance is lost because MOS transistors become slower at lower operating voltages.
 The main reason is that the threshold voltages of the transistors do not scale accordingly with the
operating voltage to avoid excessive leakage current.
 Noise immunity is also a concern at low voltage swing.
 Special level converters are required to interface low swing signals to the full-swing ones.
Reduce Capacitance
 Reducing parasitic capacitance in digital design has always been a good way to improve performance
as well as power.
 However, a blind reduction of capacitance may not achieve the desired result in power dissipation.

 The real goal is to reduce the product of capacitance and its switching frequency.

 Signals with high switching frequency should be routed with minimum parasitic capacitance to
conserve power.
 Conversely, nodes with large parasitic capacitance should not be allowed to switch at high frequency.

 Capacitance reduction can be achieved at most design abstraction levels:

material, process technology, physical design (floor planning, placement and routing), circuit techniques,
transistor sizing, logic restructuring, architecture transformation and alternative computation algorithms.
Reduce Switching Frequency
 For the sake of power dissipation, the techniques for reducing switching frequency
 have the same effect as reducing capacitance.
 Again, frequency reduction is best applied to signals with large capacitance.
 The techniques are often applied to logic level design and above.
 Those applied at a higher abstraction level generally have greater impact.

 Reduction of switching frequency also has the side effect of improving the reliability of a chip as
some failure mechanism is related to the switching frequency.
Method of reducing switching frequency:
 To eliminate logic switching that is not necessary for computation.
 Alternate logic implementation: since there are many ways to design a logic network to perform
an identical function.
 The use of different coding methods, number representation systems, counting sequences and
data representations can directly alter the switching frequency of a design.
Reduce Leakage and Static Current
o Leakage current, whether reverse biased junction or sub-threshold current, is generally not very
useful in digital design.
o However, designers often have very little control over the leakage current of the digital circuit.
o Fortunately, the leakage power dissipation of a CMOS digital circuit is several orders of magnitude
smaller than the dynamic power.

 The leakage power problem mainly appears in very low frequency circuits or ones with "sleep
modes" where dynamic activities are suppressed.
 Most leakage reduction techniques are applied at low-level design abstraction such as process,
device and circuit design.
 Memory chips that have very high device density are most susceptible to high leakage power.

o Static current can be reduced by transistor sizing, layout techniques and careful circuit design.
o Circuit modules that consume static current should be turned off if not used.
o Sometimes, static current depends on the logic state of its output and we can consider reversing
the signal polarity to minimize the probability of static current flow.