Static Timing Analysis

• Static timing analysis verifies circuit timing by “adding up propagation delays

along paths between clocked elements” in a circuit.
• It checks the delays along each path against the specified timing constraints for
each circuit path and reports any existing timing violations.
Static timing analysis tools can determine and report timing statistics such as the
total number of paths, delays for each path and the circuit’s most critical paths.
• As design complexity increases, performing timing analysis manually becomes
extremely difficult and sometimes even impossible.
• To summarize, both static and dynamic timing analysis methods offer tradeoffs.
One is not a replacement for the other.
• However, the static timing analysis method offers more complete coverage, little
overhead, and the ability to report errors in terms of the design schematic.
Static Timing Analysis

• Advantages:
1.It resembles manual analysis methods.
2. It is path oriented and finds all setup and hold violations.
3. It does not require stimulus or functional models.
4. It is faster than simulation. (for the same amount of coverage).
Disadvantages:
1. It can report false errors. It cannot detect timing errors related to
logical operation
2. it cannot detect timing errors, such as race conditions, that are
based on the logical operation of the circuit.
Static Timing Analysis

• Static timing analysis is similar to manual analysis process, except

that it is automated. This allows the design to be analyzed much
faster. This makes it possible for a designer to experiment with
different synthesis options and constraints in a short time.
• This method is also complete because it traces and evaluates all paths
in a design, not just those exercised by test stimulus.
• Because static timing analysis does not perform logic simulation, test
stimulus and functional models are not required.
• This makes static analysis available earlier since development time for
stimulus and models are not required.
Static Timing Analysis

• The modeling requirements for a static analysis tool are relatively

simple.
• However, timing information for each component in the design is
required and the designer must specify waveform information about the
input data and clock signals the design uses.
• Such timing information typically include: pin-to-pin delays, setup, hold
time specifications and signal inversion information, and clock
frequency constraints.
• By checking all possible paths in a design, static timing analysis ensures
that all possible setup and hold violations in the circuit have been found.
Dynamic timing
• Dynamic timing analysis uses simulation vectors to verify that the circuit
computes accurate results from a given input without any timing
violations.
• The problem is that the simulations vector can not guarantee 100%
coverage.
• The goal for the dynamic analysis is to get a 100% coverage.
• Dynamic timing simulation is still preferred for non-synchronous logic
style.
• As a rule, however, only dynamic timing verification tools support glitch
detection and race conditions, since these are inherently dynamic events.