ADITYA ENGINEERING COLLEGE (A)

Digital Circuits and Logic Design

Sequential Circuits
By

B.V.V.L.KALA BHARATHI
Dept of ELECTRICAL AND ELECTRONICS ENGINEERING
Aditya Engineering College(A)
Surampalem.
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Digital logic circuits:

• Digital Circuits operate on digital concept 0’s and 1’s.(switch ON
&OFF).
If this job of switching is done on the application of certain logic ,then it
is called Digital logic circuit.
Two types:
Combinational logic circuits

Sequential logic circuits

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Sequential Circuits
• Combinational Logic:
• Output depends only on current input
• Able to perform useful operations (add/subtract/multiply/…)
• Has no memory

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Sequential Circuits (cont.)

• Sequential Logic:
• Output depends not only on current input but also on past input values, e.g.,
design a counter
• Need some type of memory to remember the past input values

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Sequential Circuits (cont.)

Circuits that we Information Storing
have learned Circuits
so far

Timed “States”
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Sequential Logic: Concept

• Sequential Logic circuits remember past inputs and
past circuit state.
• Outputs from the system are
“fed back” as new inputs
• With gate delay and wire delay
• The storage elements are circuits that are capable of
storing binary information: memory.

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Synchronous vs. Asynchronous

There are two types of sequential circuits:

• Synchronous sequential circuit: circuit output changes only
at some discrete instants of time. This type of circuits
achieves synchronization by using a timing signal called the
clock.
• Asynchronous sequential circuit: circuit output can change at
any time (clockless).

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Clock Signal

Clock generator: Periodic train of clock pulses

Different duty cycles

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Synchronous Sequential Circuits:

Flip flops as state memory

 The flip-flops receive their inputs from the combinational circuit

and also from a clock signal with pulses that occur at fixed
intervals of time, as shown in the timing diagram.

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SR Latch (NOR version)
0 S
S R Qn Qn+1
Qn 0
0 0 0 0
0 0 1
0 1 0
Q’n 1
0 R 0 1 1
1 0 0
1 0 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
0 S
S R Qn Qn+1
Qn 1
0 0 0 0
0 0 1 1
0 1 0
Q’n 0
0 R 0 1 1
1 0 0
1 0 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
0 S
S R Qn Qn+1
Qn
0 0 0 0
No change
0 0 1 1
0 1 0
Q’n
0 R 0 1 1
1 0 0
1 0 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
0 S
S R Qn Qn+1
Qn 0
0 0 0 0
No change
0 0 1 1
0 1 0 0
Q’n 1
1 R 0 1 1
1 0 0
1 0 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
0 S
S R Qn Qn+1
Qn 1
0 0 0 0
No change
0 0 1 1
0 1 0 0
Q’n 0
1 R 0 1 1 0
1 0 0
1 0 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
0 S
S R Qn Qn+1
Qn
0 0 0 0
No change
0 0 1 1
0 1 0 0 Reset
Q’n
1 R 0 1 1 0
1 0 0
1 0 1
X Y NAND
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
1 S
S R Qn Qn+1
Qn
0 0 0 0 0
No change
0 0 1 1
0 1 0 0 Reset
Q’n 1
0 R 0 1 1 0
1 0 0 1
1 0 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
1 S
S R Qn Qn+1
Qn
1 0 0 0 0
No change
0 0 1 1
0 1 0 0 Reset
Q’n 0
0 R 0 1 1 0
1 0 0 1
1 0 1 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
1 S
S R Qn Qn+1
Qn
0 0 0 0
No change
0 0 1 1
0 1 0 0 Reset
Q’n
0 R 0 1 1 0
1 0 0 1 SET
1 0 1 1
X Y NOR
00 1 1 1 0
01 0 1 1 1
10 0
11 0

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SR Latch
1 S
S R Qn Qn+1
Qn
0 0 0 0 0
No change
0 0 1 1
0 1 0 0 Reset
Q’n 0
1 R 0 1 1 0
1 0 0 1 SET
1 0 1 1
X Y NOR
00 1 1 1 0 Qn+1 = Q’n+1
01 0 1 1 1
Qn+1 = Q’n+1 = 0
10 0
11 0

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SR Latch
1 S
S R Qn Qn+1
Qn
1 0 0 0 0
No change
0 0 1 1
0 1 0 0 Reset
Q’n 1
1 R 0 1 1 0
1 0 0 1 SET
1 0 1 1
X Y NOR
00 1 1 1 0 Qn+1 = Q’n+1
01 0 1 1 1 (UNDEFINED)
Qn+1 = Q’n+1 = 1
10 0
11 0

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 SR Latch with Clock signal

Latch is sensitive to input changes ONLY when C=1

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D Latch
• One way to eliminate the undesirable indeterminate state in the RS flip
flop is to ensure that inputs S and R are never 1 simultaneously. This is
done in the D latch:

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Flip-Flops
• Latches are “transparent” (= any change on the inputs is seen at the
outputs immediately).
• This causes synchronization problems.
• Solution: use latches to create flip-flops that can respond (update)
only on specific times (instead of any time).
• Types: RS flip-flop and D flip-flop

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Master-Slave D Flip Flop
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Consider two latches combined together

Only one C value active at a time
Output changes on falling edge of the clock

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Master-Slave FF configuration
using SR latches

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 Master-Slave FF configuration
using SR latches (cont.)
S R CLK Q Q’
•When C=1, master is enabled and
0 0 1 Q0 Q0 ’ Store stores new data, slave stores old
0 1 1 0 1 Reset data.
1 0 1 1 0 Set •When C=0, master’s state passes
1 1 1 1 1 Disallowed to enabled slave, master not
X X 0 Q0 Q0’ Store sensitive to new data (disabled).

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Clocking Event
What if the output only changed on a C transition?

Positive edge triggered

D C Q Q’
D Q 0 0 1
1 1 0
C Q’ X 0 Q0 Q0’

NEGATIVE edge POSITIVE edge

8/24/20 TRIGGERING digital circuits and logicTRIGGERING
devices
Positive Edge-Triggered J-K Flip-Flop

J K CLK Q Q’
Created from D flop
J sets
K resets 0 0 ­ Q0 Q0’
J=K=1 -> invert output 0 1 ­ 0 1
1 0 ­ 1 0
1 1 ­ TOGGLE

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Clocked J-K Flip Flop
Two data inputs, J and K
J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

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Positive Edge-Triggered T Flip-Flop

Created from D flop

T=0 -> keep current T C Q Q’
K resets
T=1 -> invert current
0 ­ Q 0 Q0’
1 ­ TOGGLE

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 Asynchronous Inputs

• J, K are synchronous inputs

o Effects on the output are synchronized with the CLK input.
• Asynchronous inputs operate independently of the synchronous inputs and clock
o Set the FF to 1/0 states at any time.

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THANK YOU

Digital circuits and logic

design digital circuits and logic devices 8/24/20