VLSI Design and Modeling System

Chapter-5
VLSI Design
 Lecture #1

VLSI Design Style

 Combinational Circuit
• Chip Design styles (3- Basic Design Style)
1. Full-custom design
2. Semi- custom design
3. Programmable Logic Array
Programmable Logic Device (PLD)
Field Programmable Gate Array (FPGA)
Gate Array
 Full Custom Layout Design
• This means the complete physical design
layout is done manually. Even the cells or
libraries are done manually. This method is
mainly used if NRE cost comes out to be very
low. 
• Flexibility to create your own structures and
polygons in the layout. example :standard cell
 Full Custom Layout Design
• Cell Design
• Cell Verification
• Cell Functional Model
• Cell Abstract
• Design Layout and Verification
 Cell Design
• The following example details a transistor
circuit for a CMOS inverter together with its
associated mask level layout
 Cell Verification
• The designer will be required to specify
appropriate signal and power supply sources to
test the cell in all its operating modes.
 Cell Functional Model
• The following text details a typical Verilog
functional model for the CMOS inverter.
  Cell Abstract
• The cell abstract is generated from the cell
layout. It consists only of a cell outline with
contact points for the power supply
connections and the cell inputs and outputs.
 Design Layout and Verification
 Semi custom Layout Design
Semi custom VLSI design can be
– Cell based or
– Array based

In cell based design, the designer reuses the cells that

have already been designed and stored in the library
as a part of the current design.

In array based design, the designer is provided with a

chip consisting of configurable logic blocks as generic
building blocks. 
Semi-custom Layout Design
 Lecture #2

Programmable Logic Array(PLA)

• Programmable Logic Device (PLD)

• Field Programmable Gate Array (FPGA)
• Gate Array
 Programmable Logic Device(PLD)

• Programmable logic devices (PLDs) have all

but replaced special-purpose logic devices
such as AND gates, flip-flops, counters,
multiplexers, etc.
• PLDs are chips that can be programmed, and
often re-programmed, to implement different
logic functions.
 Programmable Logic Device(PLD)

• Advantage is that design with PLDs is faster

and this reduces the time required to bring a
product to market.
• Disadvantages to using programmable logic.
Design with PLDs requires additional
development software and hardware which is
often very expensive.
 Example of Programmable Logic
Device(PLD)

Programmable Arrays
• OR Array
• AND Array
Programmable Logic Device(PLD)

Programmable Array
Programmable Logic Device(PLD)

Programmable Array
Programmable Logic Devices (PLD)
Classifications of Programmable Logic Devices
(PLD)
• Programmable Read-Only Memory (PROM)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)
• Generic Array Logic (GAL)
Design the following functions using ‘PLA’
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

21
PLA implementation
F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’

AB

AC

BC

A’B’C
’

22
Design the following functions using ‘PLA’ architecture:
PAL Operation
PAL Operation
Diagram of a Programmed PAL
Output Logic