Memory and Memory

Interfacing

Ajay Singh Raghuvanshi

Memory
 Memory consists of a number of storage locations,
each of which is identified by a unique address
 The ability of the CPU to identify each location is
known as its addressability
 Each location stores a word i.e. the number of bits
that can be processed by the CPU in a single
operation. Word length may be typically 8,16, 24,
32, 64 or as many as 128 bits.
 Memory Can be classified into two categories
 RAM
 ROM
 Types of RAM memory

 Static Random Access Memory (SRAM)

Doesn’t need refreshing ,Retains contents as long as power applied to the chip
Access time around 10 nanoseconds, Can be Used for cache memory
 Dynamic Random Access Memory (DRAM)
Contents are constantly refreshed 1000 times per second
Access time 60 – 70 nanoseconds
 Synchronous Dynamic Random Access Memory (SDRAM)
Quicker than DRAM
Access time less than 60 nanoseconds
 Direct Rambus Dynamic Random Access Memory (DRDRAM)
New type of RAM architecture
Access time 20 times faster than DRAM, More expensive
 Cache memory
Small amount of memory typically 256 or 512 kilobytes
Temporary store for often used instructions Faster for CPU to access than main memory
Level 1 cache is built within the CPU (internal) Level 2 cache may be on chip or nearby
(external)
Types of ROM
Programmable Read Only Memory (PROM)
Empty of data when manufactured
May be permanently programmed by the user
Erasable Programmable Read Only Memory (EPROM)
Can be programmed, erased and reprogrammed
 The EPROM chip has a small window on top allowing it to be
erased by shining ultra-violet light on it
Afterreprogramming the window is covered to prevent new
contents being erased
Access time is around 45 – 90 nanoseconds
Types of ROM
 Electrically Erasable Programmable Read Only Memory
(EEPROM)
 Reprogrammed electrically without using ultraviolet light
 Must be removed from the computer and placed in a special machine to
do this
 Access times between 45 and 200 nanoseconds
 Flash ROM
 Similar to EEPROM
 However, can be reprogrammed while still in the computer
 Easier to upgrade programs stored in Flash ROM
 Used to store programs in devices e.g. modems
 Access time is around 45 – 90 nanoseconds
 Typical RAM chip

Chip select 1 CS1

Chip select 2 CS2
Read RD 128 x 8 8-bit data bus
RAM
Write WR
7-bit address AD 7

CS1 CS2 RD WR Memory function State of data bus

0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x

Typical ROM chip

Chip select 1 CS1
Chip select 2 CS2
512 x 8 8-bit data bus
ROM
9-bit address AD 9
Memory Interfacing
MEMORY ADDRESS MAP
 Address space assignment to each
memory chip on a me
 Example:

Hexa Address bus

Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
1 x x x x x x x x x
ROM 0200 - 03FF
The 74LS138, 3-to-8 line decoder
Example: Design a 64K-8 EPROM interface for the 8086 microprocessor
using EPROM chips (8K x 8). The ROM memory starts at address F0000H-
FFFFFH.
Assignment 2
 Design memory interface to be used with
MPU 8086 in Minimum mode with
following specifications
 ROM : 128 K: using 8 ROM chips of same size
 RAM : 256 K: using 8 RAM chips of same size
Draw the memory map of the system showing
the chip address range for each chip
 Memory Map For problem

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Range Chip No

1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0000
ROM1

1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 F0FFF

1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 F1000
ROM2

1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 F1FFF

1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 F2000
ROM3

1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 F2FFF

1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 F3000
ROM4

1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F3FFF

1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F4000
ROM5

1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 F4FFF

1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 F5000
ROM6

1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 F5FFF

1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 F6000
ROM7

1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 F6FFF

1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 F7000
ROM8

1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F7FFF

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F8000
RAM1

1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 F8FFF

1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 F9000
RAM2

1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 F9FFF

1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FA000
RAM3

1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 FAFFF

1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 FB000
RAM4

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FBFFF

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC000
RAM5

1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 FCFFF

1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 FD000
RAM6

1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 FDFFF

1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FE000
RAM7

1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 FEFFF

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 FF000
RAM8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFF