Computer Organization and

Assembly Language
CPT213: Lecture Slides 1
Objectives

In this slides, you will learn about the following:

 The components of a computer system

 Putting all the pieces together—the Von

Neumann architecture

 Non-Von Neumann architectures

2
Introduction

 Computer organization examines the computer

as a collection of interacting “functional units”

 Functional units may be built out of the circuits

already studied

 Higher level of abstraction assists in

understanding by reducing complexity

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Figure 1.1
The Concept
of Abstraction

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The Components of a Computer
System
 Von Neumann architecture has four functional
units
 Memory
 Input/Output
 Arithmetic/Logic unit
 Control unit
 Sequential execution of instructions
 Stored program concept
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 Figure 1.2
Components of the Von Neumann Architecture

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Memory and Cache

 Information stored and fetched from memory

subsystem

 Random access memory maps addresses to

memory locations

 Cache memory keeps values currently in use in

faster memory to speed access times

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Memory and Cache (continued)

 RAM (random access memory)

 Memory made of addressable cells
 Current standard cell size is 8 bits
 All memory cells accessed in equal time
 Memory address
 Unsigned binary number N long
 Address space is then 2N cells

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 Figure 1.3
Structure of Random Access Memory

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Main Memory

Unit Exact Number of bytes Approximation

------------ ------------------------ ------------
kilobyte 210 bytes 103 bytes
megabyte 220 bytes 106 bytes
gigabyte 230 bytes 109 bytes
terabyte 240 bytes 1012 bytes
petabyte 250 bytes 1015 bytes
exabyte 260 bytes 1018 bytes

Table 5.1 Memory units

Address as bit pattern

Note:

Memory addresses are defined using

unsigned binary integers.
Example 1
A computer has 32 MB (megabytes) of memory.
How many bits are needed to address any single
byte in memory?
Solution
The memory address space is 32 MB, or 2 25 (25
x 220). This means you need log2 225 or 25 bits,
to address each byte.
Example 2
A computer has 128 MB of memory. Each word
in this computer is 8 bytes. How many bits are
needed to address any single word in memory?
Solution
The memory address space is 128 MB, which
means 227. However, each word is 8 (23) bytes,
which means that you have 224 words. This
means you need log2 224 or 24 bits, to address
each word.
Memory and Cache (continued)

 Parts of the memory subsystem

 Fetch/store controller
 Fetch: Retrieve a value from memory
 Store: Store a value into memory
 Memory address register (MAR)
 Memory data register (MDR)
 Memory cells with decoder(s) to select individual
cells

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Memory and Cache (continued)

 Fetch operation

 The address of the desired memory cell is moved

into the MAR

 Fetch/store controller signals a fetch, accessing

the memory cell

 The value at the MAR’s location flows into the

MDR

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Memory and Cache (continued)

 Store operation

 The address of the cell where the value should go

is placed in the MAR

 The new value is placed in the MDR

 Fetch/store controller signals a store, copying the

MDR’s value into the desired cell

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Memory and Cache (continued)

 Memory register

 Very fast memory location

 Given a name, not an address

 Serves some special purpose

 Modern computers have dozens or hundreds of

registers

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Cache Memory

 Memory access is much slower than processing

time
 Faster memory is too expensive to use for all
memory cells
 Locality principle
 Once a value is used, it is likely to be used again
 Small size, fast memory just for values currently
in use speeds computing time

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Input/Output and Mass Storage

 Communication with outside world and external

data storage

 Human interfaces: Monitor, keyboard, mouse

 Archival storage: Not dependent on constant

power

 External devices vary tremendously from each

other

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Input/Output and Mass Storage
(continued)
 Volatile storage
 Information disappears when the power is turned
off
 Example: RAM
 Nonvolatile storage
 Information does not disappear when the power is
turned off
 Example: Mass storage devices such as disks,
flash and tapes
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Input/Output and Mass Storage
(continued)
 Mass storage devices
 Direct access storage device
 Hard drive, CD-ROM, DVD
 Uses its own addressing scheme to access data
 Sequential access storage device
 Tape drive
 Stores data sequentially
 Used for backup storage these days

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Input/Output and Mass Storage
(continued)
 Direct access storage devices
 Data stored on a spinning disk
 Disk divided into concentric rings (tracks)
 Read/write head moves from one track to another
while disk spins
 Access time depends on:
 Seek time: time needed to position head over track
 Latency: time needed for sector to rotate to head
 Transfer time: time for sector to be read by head

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 Figure 1.4
Overall Organization of a Typical Disk

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Input/Output and Mass Storage
(continued)
 I/O controller
 Intermediary between central processor and I/O
devices

 Processor sends request and data, then goes on

with its work

 I/O controller interrupts processor when request is

complete

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 Figure 5.9
Organization of an I/O Controller

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The Arithmetic/Logic Unit

 Actual computations are performed

 Primitive operation circuits
 Arithmetic (ADD)
 Comparison (CE)
 Logic (AND)
 Data inputs and results stored in registers
 Multiplexor selects desired output

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The Arithmetic/Logic Unit
(continued)
 ALU process
 Values for operations copied into ALU’s input
register locations
 All circuits compute results for those inputs
 Multiplexor selects the one desired result from all
values
 Result value copied to desired result register

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 Figure 1.5
Using a Multiplexor Circuit to Select the Proper ALU Result

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The Control Unit

 Manages stored program execution

 Task
 Fetch from memory the next instruction to be
executed

 Decode it: Determine what is to be done

 Execute it: Issue appropriate command to ALU,

memory, and I/O controllers

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Machine Language Instructions

 Can be decoded and executed by control unit

 Parts of instructions
 Operation code (op code)
 Unique unsigned-integer code assigned to each
machine language operation
 Address fields
 Memory addresses of the values on which
operation will work

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 Pentium Machine Language Instruction Format
Figure 5.14
Typical Machine Language Instruction Format

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Machine Language Instructions
(continued)
 Operations of machine language
 Data transfer operations
 Move values to and from memory and registers

 Arithmetic/logic operations
 Perform ALU operations that produce numeric
values

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Machine Language Instructions
(continued)
 Operations of machine language (continued)
 Compare operations
 Compare two values and set an indicator on the
basis of the results of the compare; set register bits

 Branch operations
 Jump to a new memory address to continue
processing

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Control Unit Registers and Circuits
 Parts of control unit
 Links to other subsystems
 Instruction decoder circuit
 Two special registers
 Program counter (PC)
 Stores the memory address of the next instruction to
be executed
 Instruction register (IR)
 Stores the code for the current instruction

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 Figure 1.6
Organization of the Control Unit Registers and Circuits

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Putting All the Pieces Together—the
Von Neumann Architecture
 Subsystems connected by a bus

 Bus: Wires that permit data transfer among them

 At this level, ignore the details of circuits that

perform these tasks: Abstraction!

 Computer repeats fetch-decode-execute cycle

indefinitely

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Figure 1.8
The Organization
of a Von Neumann
Computer

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Non-Von Neumann Architectures

 Physical limitations on speed of Von Neumann

computers

 Non-Von Neumann architectures explored to

bypass these limitations

 Parallel computing architectures can provide

improvements; multiple operations occur at the
same time

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Non-Von Neumann Architectures
(continued)
 SIMD architecture
 Single instruction/multiple data
 Multiple processors running in parallel
 All processors execute same operation at one
time
 Each processor operates on its own data
 Suitable for vector operations
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 Figure 1.9
A SIMD Parallel Processing System

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Non-Von Neumann Architectures
(continued)
 MIMD architecture

 Multiple instruction/multiple data

 Multiple processors running in parallel

 Each processor performs its own operations on its

own data

 Processors communicate with each other

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 Figure 1.10
Model of MIMD Parallel Processing

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Summary
 Computer organization examines different
subsystems of a computer: memory,
input/output, arithmetic/logic unit, and control
unit
 Machine language gives codes for each primitive
instruction the computer can perform and its
arguments
 Von Neumann machine: Sequential execution of
a stored program
 Parallel computers improve speed by doing
multiple tasks at one time

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