Chapter 10 Digital Integrated

Circuits

10-1 Introduction

10-2 Special Characteristics

10-3 Bipolar-Transistor Characteristics

10-4 RTL and DTL Circuits

10-5 Transistor -Transistor Logic
Chapter 10 Digital Integrated
Circuits

10-6 Emitter-Coupled Logic

10-7 Metal-Oxide Semiconductor (MOS)

10-8 Complementary MOS (CMOS)

10-9 CMOS Transmission Gate Circuits

10-10 Switch-Level Modeling With HDL
 10-1 Introduction

RTL ( Resistor-transistor logic)

DTL ( Diode-transistor logic)
TTL ( Transistor-transistor logic)
IC digital
logic family ECL ( Emitter-coupled logic)
MOS ( Metal-oxide semiconductor)
CMOS ( Complementary metal-
oxide semiconductor)
 10-1 Introduction

NAND gate

If any input of a NAND gate is low, the output is high.

If all inputs of a NAND gate are high, the output is low.
 10-1 Introduction

NOR gate

If any input of a NOR gate is high, the output is low.

If all inputs of a NOR gate are low, the output is high.
 10-2 Special Characteristics

Fan-Out
The fan-out of a gate specifies the number of
standard loads that can be connected to the
output of the gate without degrading its normal
operation.
The fan-out is calculated from the amount of
current available in the output of a gate and the
amount of current needed in each input of a gate.
 10-2 Special Characteristics
Fan-Out
The fan-out of the gate is calculated from the ratio
IOH/IIH or IOL/IIL, whichever is smaller.
 10-2 Special Characteristics

Power Dissipation
The power dissipation is a parameter
The current thatfrom
that is drawn
The current that is drawn from
represents the amount of power
the power supply needed
when thebyoutput
the
the power supply when the output
gate. of the gate is in the low-voltage
of the
Thegate is in
power is the
the high-voltage
product VCC × ICC .
level
level
The current drain from the power supply depends
on the logic state of the gate.
Supply voltage
The current
The average current is ICC (avg) = ( ICCHthat is ) /2
+ ICCL
drawn by the circuit.
 10-2 Special Characteristics

Power Dissipation
The average power dissipation
PD (avg) = ICC (avg) × VCC

In a typical digital system there will be many IC,

and the power required by each IC must be
considered. The total power dissipation in the
system is the sum total of the power dissipated in
the all ICs.
 10-2 Special Characteristics

Propagation Delay
The propagation delay of a gate is the average
transition-delay time for the signal to propagate
from input to output when the binary signal
changes in value.
The signal-delay time
between the input and
output when the
output changes from
the high to the low
level is referred to as
tPHL
 10-2 Special Characteristics

Propagation Delay
The propagation delay of a gate is the average
transition-delay time for the signal to propagate
from input to output when the binary signal
changes in value.
When the output goes
from the low to the
high level, the delay
is tPLH
 10-2 Special Characteristics

Noise Margin
Noise is a term used to denote an undesired signal
that is superimposed upon the normal operating
signal.

Noise margin is the maximum noise voltage added

to an input signal of a digital circuit that does not
cause an undesirable change in the circuit output
 10-2 Special Characteristics

Noise Margin

Noise margin is
the difference VOH
-VIH or VIL -VOL ,
whichever is
smaller.
10-3 Bipolar-Transistor Characteristics

Current
Region VBE(V) VCE(V) Relationship
Cutoff < 0.6 Open circuit IB = IC = 0
Active 0.6-0.7 > 0.8 IC = hFEIB
Saturation 0.7-0.8 0.2 I >=I /h
B CS FE
10-3 Bipolar-Transistor Characteristics
Demonstration
Consider the inverter circuit of
the figure with the following
parameters:
RC = 1KΩ VCC = 5V
RB = 22KΩ H = 5V
hFE = 50 L = 0.2 V
 10-3 Bipolar-Transistor Characteristics
Demonstration
IB = (Vi – VBE) / RB = (5 – 0.7) /
22KΩ = 0.195mA
ICS = (VCC – VCE) / RC
= (5 – 0.2) /1KΩ = 4.8mA
0.195 = IB >= ICS/hAssuming
FE = 4.8/50
VCE =0.09
=0.2V
6mA

The transistor is saturated and its

output voltage VO = VCE =0.2V= L
 10-4 RTL and DTL Circuit
RTL Basic Gate

If all inputs are low at 0.2 V, all transistors are

cut off. This causes the output of the circuit to be
high.
 10-4 RTL and DTL Circuit
RTL Basic Gate

If any input of the RTL gate is high, the

corresponding transistor is driven into saturation.
This causes the output to be low, regardless of the
states of the other transistors.
 10-4 RTL and DTL Circuit
DTL Basic Gates
If any input of the gate
is low at 0.2V, the
corresponding input
diode conducts current
through VCC and the 5K
resistor into the input
node.
The voltage of P is equal to a total of 0.9V that is not
enough to overcome the a potential of one VBE drop
plus two diode drop. The transistor is cutoff. The
output voltage is high at 5V.
 10-4 RTL and DTL Circuit

DTL Basic Gates

If all inputs are high,

the transistors is
driven into the
saturation region.
This causes the output
to be low.
 10-4 RTL and DTL Circuit

DTL Basic Gates

The fan-out of a DTL
gate may be increased
by replacing one of the
diodes in the base
circuit with a
transistor.
 10-5 Transistor -Transistor Logic

The original basic TTL gate was a slight

improvement over the DTL gate.

TTL gates have three different types of output

configuration:
1. Open-collector output
2. Totem-pole output
3. Three-state (or tristate) output
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

The basic TTL gate is a modified circuit of the DTL
gate
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

The basic TTL gate is a modified circuit of the DTL
gate
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

The basic TTL gate is a modified circuit of the DTL
gate
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

If any input is low,
the voltage at the base
of Q1 is equal to 0.9V.
In order for Q3 to 0.9V
start conducting, the 0.2V
voltage at the the base 1.8V
of Q1 must be greater
than 1.8V.
Therefore, the output
transistor is cutoff.
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

If all input are high,
both Q2 Q3 conduct
and saturate. The
base voltage of Q1 is
equal to the voltage 2.1V
3V
across its base-
collector pn junction
plus two VBE drop in
The output transistor
Q2 and Q3, or 2.1V.saturates, the output
goes low to 0.2V
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

If the output of several open-
collector TTL gates are tied
together with a single external
resistor, a wired-AND logic is
performed.
The wire-AND logic gives a high
level only if all variables are high;
otherwise, the function is low.
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

The wire-AND gate is not a
physical gate, but only a
symbol to designate the
function obtained from the
indicated connection.
 10-5 Transistor -Transistor Logic

Open-Collector Output Gate

Open-collector gates can be
tied together to form a
common bus.
Three of the inputs are 0,
which produces a 1 on the
bus. The fourth input, I4, can
now transmit information
through the common-bus line
into inverter 5.
 Internal temperature
10-6 Emitter-Coupled Logic
and voltage compensated
bias network
Differential
input amplifier

Emitter-follower
outputs
 10-6 Emitter-Coupled Logic
The graphic symbol
of ECL Gate

Two outputs of two or

more ECL gates can be
connected together to
form wired logic.

Wired-OR

Wired-AND
10-7 Metal-Oxide Semiconductor (MOS)

Inverter

1. When the input voltage is low

(below VT), Q2 turns off. The
output voltage is at about
VDD.
2. When the input voltage is
high (above VT), Q2 turns on.
The output voltage is at a
voltage below VT.
10-7 Metal-Oxide Semiconductor (MOS)

NAND Gate

1. Input A and B must both be

0
high for all transistors to
conduct and cause the output 1
to go low.
2. If either input is low, the 1
corresponding transistor is
turned off and the output is
high.
10-7 Metal-Oxide Semiconductor (MOS)

NAND Gate

1. Input A and B must both be

1
high for all transistors to
conduct and cause the output 0
to go low.
2. If either input is low, the 1
corresponding transistor is
turned off and the output is
high.
10-7 Metal-Oxide Semiconductor (MOS)

NOR Gate

1. If either input is
high, the
corresponding
transistor conducts
and the output is low.
2. If all inputs are low,
all active transistors
are off and the
output is high.
 10-8 Complementary MOS (CMOS)

Inverter
1. When the input is low, both
gates are zero potential.
The input is at –VDD,
Therelative
sourceto the source
terminal of the
of the p-
p-channel device and at 0 V 0 1
channel device is at V DD
relative to the source of the
n-channel device. p-channel
device is turned on and the
The source
n-channel terminal
device of the n-
is turned
off.channel device is at ground.
 10-8 Complementary MOS (CMOS)

Inverter

2. When the input is high, both

gates are at VDD. The p-cha
nnel device is turned off an
d the n-channel device is tu 1 0
rned on.
10-8 Complementary MOS (CMOS)

NAND Gate
A two-input NAND gate
consists of two p-type units in
parallel and two n-type units 0
in serial.
1
If all inputs are high, both p-
channel transistors turn off
and both n-channel 1
transistors turn on. The
output produces a low state.
10-8 Complementary MOS (CMOS)

NAND Gate
If any input is low, the
associated n-channel
transistor is turned off and 1
the associated p-channel
1
transistor is turned on. The
output goes to the high state.
0
10-8 Complementary MOS (CMOS)

NOR Gate
A two-input NOR gate
consists of two n-type units 0
in parallel and two p-type
units in serial. 0
If all inputs are low, both 1
p-channel transistors turn
on and both n-channel
transistors turn off. The
output goes to the high
state.
10-8 Complementary MOS (CMOS)

NOR Gate
If any input is high, the
1
associated p-channel
transistor is turned off and
the associated n-channel 0
0
transistor is turned on. The
output goes to the low state.
10-8 Complementary MOS (CMOS)

COMS Characteristics

•Low power dissipation

•Greater packing density
•Good noise immunity
•Reasonable propagation delay
10-9 CMOS Transmission Gate Circuits

A transmission gate consists

of one n-channel and one p-
0
channel MOS transistor
connected in parallel.
When the N gate is at ground
and P gate at VDD, both
transistors are off and there 1
is an open circuit between X
and Y.
10-9 CMOS Transmission Gate Circuits

When the N gate is at VDD and 1

P gate at ground, both
transistors are on and there is
an close circuit between X
and Y.
0

The block diagram of

the transmission gate
10-9 CMOS Transmission Gate Circuits

The transmission gate

is usually connected to
an inverter and
referred to as a bilateral
switch.

•When C=1, the switch is closed;

•when C=0, the switch is open.
10-9 CMOS Transmission Gate Circuits
The block diagram of
Exclusive-OR Constructed
Exclusive-ORConstructed with Gates
with Transmission
Transmission Gates

The truth table of

Exclusive-OR Constructed
with Transmission Gates
10-9 CMOS Transmission Gate Circuits
0
Multiplexer 0
with
Transmission
Gates
10-9 CMOS Transmission Gate Circuits
Gated D Latch with Transmission
Gates

Q=D
10-9 CMOS Transmission Gate Circuits
Gated D Latch with Transmission
Gates
Q retains its
present state.
0
10-10 Switch-Level Modeling with HDL

Inverter
//CMOS inverter Fig. 10-22 (a)
module inverter (Y,A);
input A;
output Y;
supply1 PWR; Define the
supply0 GRD; power and
pmos (Y,PWR,A); //(Drain,source,gate)
nmos (Y,GRD,A); //(Drain,source,gate)
ground with the
endmodule keywords
supply1 and
supply0
10-10 Switch-Level Modeling with HDL

Inverter
//CMOS inverter Fig. 10-22 (a)
module inverter (Y,A);
input A;
output Y;
supply1 PWR; Instantiate a
supply0 GRD; PMOS and a
pmos (Y,PWR,A); //(Drain,source,gate)
nmos (Y,GRD,A); //(Drain,source,gate)
NMOS
endmodule
10-10 Switch-Level Modeling with HDL

Inverter
//CMOS inverter Fig. 10-22 (a) The output and
module inverter (Y,A);
the input are
input A;
output Y; common to
supply1 PWR; both transistors
supply0 GRD; at their drain
pmos (Y,PWR,A); //(Drain,source,gate) and gate
nmos (Y,GRD,A); //(Drain,source,gate) terminals,
endmodule
respectively.
 10-10 Switch-Level Modeling with HDL

NAND Gate
//CMOS 2-input NAND Fig. 10-22(b)
module NAND2 (Y,A,B); Two PMOS
input A,B; transistors
output Y;
connected in
supply1 PWR;
supply0 GRD; parallel with
wire W1; //terminal between two nmos their source
pmos (Y,PWR,A); //source connected to Vdd terminal
pmos (Y,PWR,B); // parallel connection
nmos (Y,W1,A); // serial connection
connected to
nmos (W1,GRD,B); // source connected to ground PWR.
endmodule
 10-10 Switch-Level Modeling with HDL

NAND Gate
//CMOS 2-input NAND Fig. 10-22(b)
module NAND2 (Y,A,B); Two NMOS
input A,B; transistors
output Y; connected in
supply1 PWR;
supply0 GRD; serial with a
wire W1; //terminal between two nmos common
pmos (Y,PWR,A); //source connected to Vdd terminal W1.
pmos (Y,PWR,B); // parallel connection
nmos (Y,W1,A); // serial connection
nmos (W1,GRD,B); // source connected to ground
endmodule
 10-10 Switch-Level Modeling with HDL

Circuits with Transmission Gate

//XOR with CMOS switchs Fig. 10-25
module SXOR (A,B,Y); Transmission
input A,B;
output Y; gate
wire Anot, Bnot; description
//instantiate inverter
inverter v1 (Anot,A);
inverter v2 (Bnot,B);
//instantiate cmos switch
cmos (Y,B,Anot,A); //(output,input,ncontrol,pc
ontrol)
cmos (Y,Bnot,A,Anot);
endmodule
 10-10 Switch-Level Modeling with HDL
Continued
//CMOS inverter Fig. 10-22(a) //Instantiate SXOR
module inverter (Y,A); SXOR X1 (A,B,Y);
input A; //Apply truth table
output Y; initial
supply1 PWR; begin
supply0 GRD; A=1'b0; B=1'b0;
pmos (Y,PWR,A); //(Drain,s #5 A=1'b0; B=1'b1;
ource,gate) #5 A=1'b1; B=1'b0;
nmos (Y,GRD,A); //(Drain,s #5 A=1'b1; B=1'b1;
ource,gate) end
endmodule //display results
//Stimulus to test SXOR initial
module test_SXOR; $monitor ("A =%b B= %b Y
reg A,B; =%b",A,B,Y);
wire Y; endmodule