Verification of “Advanced

Encryption Standard”

Author: Nadav Talmon

Academic Supervisor: Prof. Joel Ratzabi
Academic Engineer: Mr. Buskila Meir
Head of Verification team: Mr. Lior Festinger
Head of Hardware team: Mr. David Darmon
Presentation Date: 06.11.19
 Introduction
• L&T Technology Services

• AES Features

• AES Verification Goals

 L&T Technology Services
• L&T Technology Services is a global leader
in Engineering and Research and
Development services.
• Innovations speak for itself – world’s 1st
Autonomous Welding Robot, Solar
‘Connectivity’ drone, and smartest campus
in the world.
• LTTS is a operating in over thirty countries
and its estimated worth is eighteen billion
dollars.
 AES Features
• Supports full AES encryption/decryption, AES encryption only and AES decryption only.

• 20 clock cycles for 128bit encryption- 6.4 bits per cycle.

• Supports 32/64/128-bit busses.

• Supports 128/256-bit key length.

• Supports CBC and ECB cypher modes.

• Simple interface.
 AES Verification Goals

• Correctness of design according to specification

• Integration support for customers which includes

o Test suite
o Documentation
o Full UVM environment for integration
 Active Agent (IP level)
 Passive Agent (Integration)
 Background

• Verification Methodology
 Verification Methodology
Coverage plan, Functional Coverage,
Environment Architecture Random Generator,
Scoreboard,
SVAs,
Direct tests

Functional coverage

Verification Code coverage

Running &
Environment
Requirements Test plan Debug
Development
Gate level
Simulation reports

Bug report
 Coverage

• Coverage Plan

• Functional Coverage and Code Coverage

• Rank List Vs. Run List

Coverage Plan
Functional Coverage and Code Coverage
Code Coverage
Tells how well HDL code has been exercised by
your test bench
Functional Coverage
Measures how well the functionality of the design
has been covered by your test bench.
User has to define the functionality to be
measured through coverage

Verifies completeness of verification environment Verifies completeness of verification environment

in terms of hitting expression lines of RTL code as per the requirements specification and also
functional coverage points

Does not use design specification Use design specification

Support in all languages Verilog does not support function coverage.
To do functional coverage, SystemVerilog is
needed.
 Rank List Vs. Run List
List Number of Efficient Full Space AES number
tests Coverage of tests to get
full space
coverage

Run List Max No Yes 30000

Rank List Min Yes Yes 108

 Verification Implementation

• Verification Environment Architecture

• Verification Platform

• Verification Plan
Verification Environment Architecture

AES Start Match/Mismatch

AES Data
In
Expected
AES KEY Data Out

Assertions
AES Start

AES Data
In
AES Data
AES KEY Out
 Verification Platform
• Scripts
o Change package of design with new parameters per each test
 Build AES work environment
 Compile AES RTL and Verification files
 Run a specific AES test simulation
 Run a list of AES test simulations
 Collect code & functional coverage
• Tools
Tools Description

GUI Synopsys VCS DVE

Operating System Linux

Simulator Synopsys VCS

TB Language System Verilog

Methodology UVM
 Verification Plan

• Plan verification methodology, create ATP and coverage plan.

• Coding of agents, monitors, scoreboard etc.

• Verifying the design, running regressions (aka run list).

• Reach 100% functional and code coverage.

• Create RANK of tests and test suite for customer.

• Rerun RANK on gate level to check correctness.

• Provide UVM verification env with passive agents, to be integrated into customers
design.
 Results
• Waves

• Coverage Results
Waves
Coverage Results
 Summary
Design goals achieved.

Verification goals achieved.

UVM environment fully implemented and working with passive/active agent.

Reached 100% Coverage.

Product is being sold in the market to various companies.

 Thank you

Author: Nadav Talmon

Academic Supervisor: Prof. Joel Ratzabi
Academic Engineer: Mr. Buskila Meir
Head of Verification team: Mr. Lior Festinger
Head of Hardware team: Mr. David Darmon
Presentation Date: 06.11.19