Professional Documents
Culture Documents
Cmos Implementation of Logic Blocks and Sequential Elements
Cmos Implementation of Logic Blocks and Sequential Elements
CMOS
Implementation
of logic blocks
and sequential
elements
Signal Strength
Strength of signal
– How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
– But degraded or weak 1
pMOS pass strong 1
– But degraded or weak 0
Thus nMOS are best for pull-down network
And, pMOS are best for pull-up network
s d g=1
g=0
s d 1 strong 1
g g g
a b a b a b
gb gb gb
EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y
EN
EN
A Y
EN
1: Circuits & Layout CMOS VLSI Design 4th Ed. 6
Tristate Inverter
Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
D0
S Y
D1
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
D0
S0 S1
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
D3
CLK CLK
D
Latch
D Q
Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
CLK
CLK = 1 CLK = 0
CLK
CLK
CLK
D
Flop
D Q
Q
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
CLK = 0
QM
D Q
CLK = 1
CLK