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Design Technology: BY Hassan Al Manasrah Tamir Al Zu'Bi
Design Technology: BY Hassan Al Manasrah Tamir Al Zu'Bi
BY
HASSAN AL MANASRAH
TAMIR AL ZU’BI
Outline
2
Introduction
Automation: synthesis
Verification: hardware/software co-simulation
Reuse: intellectual property cores
Design process models
Introduction
3
Verification Reuse
Implementation
Automation: synthesis
6
Hardware design involves many more dimensions, while compilers must generate assembly instructions to implement itself.
Hardware Designer concerned about size, power, performance and other metrics.
Synthesis Levels
9
Gajski’s Y-chart
Each axis represents type of Carry-ripple adder Addition
FSM synthesis
State minimization
State encoding
Two-level minimization
11
00
0 0 1 0 00
0 0 1 0
1 represents minterm 01
0 0 1 0 01
0 0 1 0
Circle represents implicant
11
1 0 0 0 11
1 0 0 0
10
0 0 1 0 10
0 0 1 0
Minimum cover Minimum cover
Covering all 1’s with min # of circles F=abc'd' + a'cd + ab'cd
delay
m
Solve for smallest size
Multilevel gives pareto-optimal solution
2-level minim.
Minimum delay for a given size
size
Minimum size for a given delay
Example
18
used
FSM synthesis
19
High-level synthesis
Converts single sequential program to single-purpose processor
FSDM Does not require the program to schedule states
Behavioral synthesis tool use advance techniques to carry out task
scheduling allocation.
Key sub problems
Allocation Implementing a sequential program needs
Binding
Scheduling
Assign sequential program’s operations to states
Optimizations important
Compiler
Constant propagation, dead-code elimination, loop unrolling
Advanced techniques for allocation, binding, scheduling
System synthesis
Collection of processors 23
Tasks (cont.)
Partitioning
Mapping 1 or more processes to 1 or more processors
Variables among memories
Communications among buses
Scheduling
Determining when each of the multiple processes on a single processor will have
chance to execute on the processor.
Memory accesses, bus communications must be schedule.
Verification
Verification
27
Changing the way COTS components are sold ,it is being sold as intellectual
property (IP) rather than actual IC.
Designers can integrate these descriptions with other to form one large SOC.
Processor-level components known as cores ,and it is referred to GPP or SPP IP
component.
…Cont
38
Soft core
Gajski’s Y-chart
Synthesizable behavioral
description Structural Behavioral
Typically written in HDL Processors, memories Sequential programs
(VHDL/Verilog) Registers, FUs, MUXs Register transfers
Chips
Physical description Boards
Hard cores
Ease of use
Developer already designed and tested hard core
Can use right away
Can expect to work correctly
Predictability
Size, power, performance predicted accurately
It is specific for exact IC process ,and not easily mapped (retargeted) to different process
E.g., core available for vendor X’s 0.25 micrometer CMOS process
Can’t use with vendor X’s 0.18 micrometer process
Can’t use with vendor Y
Soft cores
Can be synthesized to nearly any technology
Can optimize for particular use
E.g., delete unused portion of core which gives Lower power ,and smaller designs
Requires more design effort
May not work in technology not tested for
Not as optimized as hard core for the same processor ,since hard cores have been given more
attention.
Firm core advantages & disadvantages
40
• One price for IP and designers can make as many copies as needed
Many other models used
IP protection
The next slide
IP protection
42
IP protection has become a key concern of core providers
In the past
Illegally copying of IC is very difficult
Reverse engineering required tremendous, deliberate effort
“Accidental” copying is not possible
Today
Cores sold in electronic format
Deliberate/accidental unauthorized copying are easier
Vendors consider Safeguards greatly when selling their products
Contracts are created between vendors and designers to ensure no copying and distributing
for the IP
Encryption techniques is used by vendors to limit the actual exposure to IP
E.g. watermarking
determines if particular instance of processor was copied
whether copy authorized
New challenges to processor users
43
There are a new challenges posed for a designers to use GPP & SPP
Licensing arrangements
Purchasing a cores is not as easy as purchasing ICs
More contracts enforcing pricing model and IP protection and possibly requiring legal assistance .
Extra design effort
Especially for soft cores
Must still be synthesized and tested
Waterfall model
Compilation
Manual design
Spiral-like model
Maturation of synthesis/compilers